When you have problems with the FSB your going to need to learn about a few basic facts about memory settings here are some of the basics;
A short intro to SDRAM, penalty cycles and latencies
SDRAM (same as DDR) is not infinitely fast. DRAM consists of capacitors, gating transistors and bit lines and worldliness (data lines and address lines). Capacitors and lines need to be precharged and the address strobes need time to lock into the correct position in order to retrieve the data.
1. The typical cycle starts with a bank activate command that selects and activates one bank and row of memory through the input pins.
2. During the next cycle, the data is selected onto the data (or bit) lines and moves towards the sense amplifiers.
3. When the data bits reach the sense amplifiers the data is latched by an internal timing signal.
4. This process takes length of time called the Row Access Strobe to Column Access Strobe delay (RAS to CAS delay) with a latency of usually two or three cycles.
5. After this delay, a read command can be issued along with the column address to select the address of the first word to be read from the sense amplifiers.
6. After the read command there is a CAS delay or latency while the data is select from the sense amplifiers and clocked to the output pin. The CAS latency is typically 2 or 3 cycles. Once the data is released to the bus, another word is output every cycle until the data burst is complete.
7. Only after all the information has been output, the data can be moved back from the sense amplifiers to the row of cells to restore its contents. Movement of the data back to the empty cells again takes 2 to 3 clock cycles.
8. Depending on the leaking or bleeding of the memory cells, the quality of the charge may have to be restored during a so-called refresh cycle. The need for a recharge is determined by a refresh controller whereas the actual process of refreshing is monitored by the refresh counter. This refreshing requires additional 7-10 clock cycles during which the data flow is interrupted and, thus results in a performance hit.
The typical timing settings that decide over performance are:
SDRAM CAS Latency, CAS-DL; often called DRAM cycle time:(n cycles) number of cycles the column address strobe needs to select the correct address.
SDRAM tRAS-to-CAS Delay, tRCD; often described as Bank X/Y DRAM timing:(n cycles) number of cycles from when a bank activate command is issued until a read or write command is accepted, that is, before the CAS becomes active. In other words, after a bank activate command, the RAS lines need to be precharged before a read command (specifying the column address) can be issued. This means that the data need to be moved out of the memory cells into the sense amps which takes somewhere between 2 and 3 penalty cycles. It is important to know that tRCD only plays a minor role in the overall penalty since most reads occur as page hits, data are read out of a page already open (but see below). Unfortunately, in most BIOS, tRCD is not directly accessible, at least not under its real name but is hidden in the Bank X/Y DRAM Timing field.
SDRAM SRAS Precharge Delay: tRP (n cycles) necessary to move the data back to the cell of origin (close the bank / page) before the next bank activate command can be issued.
The weighting of different latencies
Somewhere between 30 and 60% of all read requests fall within the same page (or row) which is called a page hit. In this case, there is no need for the bank activate and tRCD, the data are already in page and the only thing that needs changing is the column address via the Column Address Strobe. Therefore, the CAS-latency becomes the most important factor in the performance of the main memory subsystem.
If the data requested are not found within the same page, the data need to be moved back to the memory cells and the bank will be closed. There are two different cases to be considered.
a. Either, the data are located in the same bank but in a different row, in this case, a precharge command needs to be issued, the bank will be closed within two or three cycles (tRP) and a new bank activate command will open the correct row (tRCD). Subsequently, a read command will select the correct column address (CAS delay). In this case, the full number of penalty cycles for CAS-DL, RAS-to-CAS and precharge will pass until the next data are output. In the case of a 2:2:2 DIMM, this will mean 6 penalty cycles, with a 3:3:3 part, the latency will increase to 9 cycles.
b. If the requested data are located in a different row, it is not necessary to wait for the first bank to close and, thus, tRP can be skipped. Consequently, the latency only comprises tRCD and CAS-DL. Precharging of the first bank (closing the page) can then occur in the background of RAS-to-CAS delay of the second bank.
It does get a bit more complicated than that. If data are contained within the same bank but in a different row, the bank needs to be closed and reactivated. In this case, the bank cycle time SDRAM tRC becomes a critical factor since every bank has a minimum time that it needs to stay open.
Bank cycle time tRC (SDRAM active to precharge time), tRAS
[5T, 7T], [7T ,9T] (Intel i815 chipset)
[5T, 7-8T], [6T ,8-9T] (VIA chipsets)
[3-10T, 4-15T] ALiMAGiK1 chipset
The bank cycle time (tRAS) specifies the number of clock cycles needed after a bank active command before a precharge can occur. In other words, after a page has been opened, it needs to stay open a minimum amount of time before it can be closed again. tRC specifies the minimum cycle time until the same bank can be reactivated. Since a precharge has a latency of 2 or 3 cycles, Trc is the sum of tRAS and RAS precharge time (tRP). The Intel i815 chipset allows for 5T,7T and 7T,9T, that is, 7 or 9 cycles bank cycle time, that is, tRP is fixed to 2T. The VIA chipsets offer tRAS values of 5T and 6T and allows to set tRP to 2 and 3 cycles, respectively but they are generally not directly accessible but part of a coctail of settings.
Most current high-end SDRAM is specified at about 50-60 ns cycle time. In turn, this means that, theoretically, at up to 133 MHz (7.5ns clock cycle), it is possible to run at a Trc of 7T (7x7.5ns=52 ns). If the clock frequency is increased, the number of cycles has to be increased, too, in order to provide the 50 ns. In other words, the theoretical limitation of the memory speed is somewhere around 183 MHz (9x6ns = 49.2ns). Interestingly, in the early revisions of the i815 chipset boards the bank cycle times were specified as [5T, 7T] and [6T, 8T] which would limit the memory bus to approximately 166 MHz.
For 100 MHz memory bus speed, in order to get best performance, the bank cycle time should be set to 5/7, for the 133 MHz memory bus, it needs to be set to 5/8 or else to 6/8, depending on how much overclocking is involved.
Why is there a minimum bank cycle time and what is tRAS violation?
After the RAS activates a bank, the data are latched onto the sense amplifiers. The way of how that works is that you have two lines, bitlines and bitlines running in parallel where one of them is the signal and the other is the reference. This is not hardwired but works like line interleaving where each line can be the signal and the other one is the reference.
The sense amplifiers sense the voltage differential (the charge released by the memory cell / capacitor onto one bitline) between the charged bitline and the reference bitline and amplify it. This signal can be relatively weak but at the same time it also needs to be restored in the memory cell. This requires amplifying the signal a bit more (up to ca. 2 V). The bitlines themselves have a certain capacitance which slows down the charging up (on average around 30-40 ns).
If a precharge occurs (to wipe all the information from the bitlines for the next bank activate (row access)), before the signal is strong enough to restore the original content in the memory cell, "tRAS is violated", resulting in loss or corruption of the data.
In other words, tRAS is the time necessary to develop the full charge of the bitlines and restore the data in the memory cells before a precharge can occur. A precharge is the command that closes the page or bank, and therefore tRAS is also defined as the minimum page open time. If you add the precharge (tRP) you end up with the total number of clocks required for opening and closing a bank, in other words the bank cycle time or tRC.
SDRAM PH limit
Refreshing is, at present, an almost negligible factor (less than 1% performance hit), however, as explained above, with increasing DIMM density, refreshing will increasingly gain importance. As mentioned above, the need for refreshing originates in the fact that capacitors lose charge and, thus, the information will expire after a certain time. The same paradigm applies to an open page since the sense amps can hold the high or low (I or O) of the information only for a limited time. In order to maintain integrity of the data, because they also have to be restored to the original memory cells, it is necessary to limit the open-time of a page. Some chipsets (BIOS) offer the option of setting the page hit limit (PH-limit), in the case of the original AMD 751 Irongate North Bridge, this limit can be selected between 8 and 64 page hits before mandatory closing of the page.
SDRAM idle cycle limit
Some BIOS interfaces offer the selection of specifying the SDRAM idle cycle limit. This means that an equivalent to the bank cycle time applies to a bank, even when it is idle. Typical settings range from 0 to 8 cycles.
Bank interleaving
One case not mentioned above was hopping from one bank to another when the respective pages are already open on each bank. This is a trick that requires high locality of the data stored in the system memory. Basically, a bank activate command can open one bank at the time and then the readout will occur after tRCD and CAS-DL. However, simultaneously, the memory controller can issue another bank activate command in the cycle after the first command was issued and, thus open the next bank. If the controller knows that the next set of data is going to be in a different bank, it can issue read commands to the next location without trashing the first bank's data burst. This way, there is the possibility to hop from one bank to another with only one penalty cycle (bank-to-bank latency) between four word bursts. In addition, precharge and bank closing can run in the background of readouts from alternating banks. Settings supported are:
a. No interleaving
b. 2-way interleaving (data are toggled between 2 banks)
c. 4 way interleaving (data are toggled between 4 banks)
As nice as this sounds, there are only specific applications that may take advantage of this feature. Specifically, any application heavily depending on the CPU cache will not be able to benefit from 2-way or 4-way interleaving, for the simple reason that the page may have expired by the time the data from the cache are exhausted. In this case, bank interleaving may even cause a performance hit since a wrong bank may be open and must be closed before the next data access.
Give it a serious read & it'll help you out.
