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what's better?

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new_novice said:
ok, what's better here:

136*9= 1224
or
130*9.5=1235

for folding of course.
I asked the same thing and was told the more Mhz the better, no matter how you get there.
 
yeah when your dealing with FSB and the multi it doesn;t matter. it is just the overall raw MHz that count.
 
i wouldnt be so fast to assume that. mhz has a big part to play in performance but the lower the multiplier the more efficent the chip runs bc it requires a higher fsb speed and this lowers the latency when it has a cache miss and needs to bring in more data from hd or main memory. in seti@home i was able to get 60 more mflops a sec out of my chip when i lowered the multi and upped the fsb (total mhz remained the same) im not saying your totally wrong bc im not really familiar with folding @home yet on my computer so im not sure what influences affect it yet
 
The higher the chip the better. However you get it there. Although the new core and newer proteins could change all that we know about this.
 
arkan said:
i wouldnt be so fast to assume that. mhz has a big part to play in performance but the lower the multiplier the more efficent the chip runs bc it requires a higher fsb speed and this lowers the latency when it has a cache miss and needs to bring in more data from hd or main memory. in seti@home i was able to get 60 more mflops a sec out of my chip when i lowered the multi and upped the fsb (total mhz remained the same) im not saying your totally wrong bc im not really familiar with folding @home yet on my computer so im not sure what influences affect it yet

many have tried to prove this and they always got the same times/speeds...
 
i got an answer from my comp. science professor it varies by the wu and the cpu if data currently being crunched fits into the cpus cache memory then over mhz win hands down but in the case of durons and celerons they run better with higher fsb bc the increased bus fequency helps them refill their pipelines and caches fast with less latency when they hit a pipeline flush or cache stall. im willing to bet this will become very evident on the new williamette celerons bc of thier lack of cache and slow default fsb.
 
arkan said:
i got an answer from my comp. science professor it varies by the wu and the cpu if data currently being crunched fits into the cpus cache memory then over mhz win hands down but in the case of durons and celerons they run better with higher fsb bc the increased bus fequency helps them refill their pipelines and caches fast with less latency when they hit a pipeline flush or cache stall. im willing to bet this will become very evident on the new williamette celerons bc of thier lack of cache and slow default fsb.

Well some have noticed that some of the newer proteins are slower now on durons compared to athlons and XPs where before they were the same. So things are changing very fast:D
 
That is true that the more memory dependent it is the more the fsb will help. In this project the memory speed hasn't been much of an issue so far, but they are making changes to the core which is what does most of the calculations so some of this remains to be seen. They have also announced that some of the new wu's are more memory dependent than in the past. I have noticed lately that my tbirds and XP's are disproportionately faster clock for clock than my durons and can only assume that this is due to the larger cache and the larger memory requirements of the work being processed. FPU still seems to be the king in determining speed, but memory could become more important in the near future.
 
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