Kissing Cousins, Not Clones . . .

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I’ve looked at the AthlonMP datasheet and having been comparing it
to the recently released Athlon Mobile datasheet. (All clips come
from one of these two documents.)

I got news for you. They may be pretty closely related, but they aren’t clones. They clearly came from a common ancestor, but then, so did men and chimps.

For instance, here’s some features of the MP that apparently aren’t in the Mobile

MP1

The Mobile chews up a lot less power than the MP at the same frequency. Look at the requirements at 1000Mhz:

Mobile Power Requirements:

MobPower

MP Power Requirements:

MPPower

OK, these matters may seem fairly academic to at least some of you.

How about determining the multiplier?

A Different Way To Choose The Multiplier

The AthlonMP uses the FID (3:0) circuits we’ve all grown to love and override.

It’s a much different story for the mobile, though.

There, the FID pins, no matter what the speed of the processor, always provide a 5X multiplier. Then the multiplier gets changed to
the “right” value using the FID_Change protocol, using different pins to indicate a change in multiplier speed is coming (SDATA [31:0]) and then the new multiplier (SDATA [36:32]).

In the Mobile, this is being used as an adjunct to Power-On technology. However, there’s no need to have Power-On technology to implement this. All that happens in the Mobile is that the CPU or software tells the mobo what speed to run, and Power-On adjusts the voltage.

Now where is the “right” value? It’s located in the “MFID field of the FidVidStatus MSR” (which AMD notes is the maximum value that software can select). What’s that? MSR stands for “Model Specific Register. It’s part of the identifiers built into the CPU. There’s no real description
in the datasheet, though apparently there’s more of one in the “Mobile AMDAthlon and Mobile AMD Duron Processor BIOS Development Application Note“, order #24141 (which is not available on AMD’s website).

Whatever it is, the AMD datasheet says that the Northbridge is required to “capture” the multiplier value. “Capture” is a funny word to use. A little later on in the document, it talks about the Northbridge doing whatever SDATA [36:32} told it to do.

(You can find all of this on pages 13-17 and 24-26 of the Athlon Mobile datasheet).

Why Should I Care?

You should care because this may prove to be AMD’s equivalent of a multiplier lock for the Palomino.

The question then becomes, “Will Palominos act like MPs, or act like Mobiles when it comes to setting the multiplier?”

AMD could play this a number of ways. The AthlonMP only has multipliers up to 12.5X. They might just leave the Palomino just that way and not provide for anything more that you can manipulate.

Or they can take the approach used by the Mobile, and the max multiplier is set by the chip. Now maybe the BIOS can override the SDATA [36,32} settings, we don’t know. If it can’t, then we have a multiplier lock.

Sort of. Unlike Intel’s “one multiplier and that’s it” lock, AMD’s only puts a maximum limit on the multiplier.

It may be still possible to make or break connections using the L1 bridges to get you a maximum multiplier of 12.5X.

Or AMD may do something else.

The purpose of this article is not to tell you that there definitely is a problem, but rather indicate that we may have a problem with the multiplier and Palominos.

They Won’t Do That!

Maybe they already have for one model of CPU already.

Have you ever wondered just how a 1.3Ghz/200Mhz tells the world it has a 13X multiplier?

It can’t do it through the FIDs, the FID for anything above 12.5X is exactly the same as for 12.5X.

The SDATA pins mentioned above are present on the TBird. The protocol isn’t documented in the TBird documentation, but then again, neither are all the items that make the pencil trick possible.

The CPU somehow has to tell the mobo that a 13X multiplier is OK, and I bet the SDATA pins have something to do with that. The mechanism may not be exactly the same as for the Mobile, but it’s likely to have some of the same elements.

More importantly, this is something that can be tested now. There’s a few mobos out there that support more than a 12.5X multiplier; the IWill KK266 being one of them.

I don’t have a KK266 handy right now, but it should be a simple enough task to try to run a TBird at 13X or 13.5X100 and see if it “takes.”

If it does, that shows that the BIOS is capable of generating a multiplier greater than 12.5X all by itself. That doesn’t guarantee it will be able to do so on a Palomino (the needed BIOS revision may remove that), but it would be a good sign.

If it can’t, then that’s not such a good sign, and an indicator that an alternate approach has to be used to get above 12.5X.

Keep in mind that an alternate approach for the Palomino might be as simple as changing FID [3:0} to FID [4:0}. Please note, though, that while the MP uses five L1 bridges, it’s only wired for FID [3:0}.

It just would seem very odd to me for AMD to have set up some sort of mechanism to get above 12.5X for TBirds and MPs and Mobiles, and then reinvent the wheel for the Palomino.

Finally, my gut tells me that this is an awfully sneaky way to slip in what boils down to a multiplier lock, and sneaky is AMD’s style.

Odder things have happened, of course, and we’ll just have to see, but keep an eye out. Don’t be an ostrich and say “it can’t happen because I don’t want it to happen.”

Email Ed

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