AMD Detailing Bulldozer at ISSCC

This week we’re being treated to some additional details regarding AMD’s upcoming Bulldozer platform when they discuss Bulldozer at ISSCC, the International Solid State Circuits Conference. There are three basic areas regarding Bulldozer being discussed (courtesy AMD).

• Design Solutions for the “Bulldozer” 32nm: Showcasing AMD’s 32nm technology and leading-edge design techniques, this session will discuss the power savings, performance improvements and new competitive features offered up by “Bulldozer”. Session date and time: Monday, 2/21, 3:15 p.m.

• 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD “Bulldozer”: This session will be used to dive even further into the Bulldozer architecture to understand its out-of-order execution set and how the integer unit performs. Session date and time: Monday, 2/21, 3:45 p.m.

• An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing: Interested in the technical and design details of “Orochi,” AMD’s upcoming high-end desktop and server processor? This session will discuss the new technologies and power-saving features used in the design. Session date and time: Tuesday, 2/22, 2:30 p.m.

As you can see, two of these have already occurred. We just got the email from AMD’s press liaison today but never fear, we haven’t missed much. They are using the Bulldozer Blog over the course of this week to lay out the new details being discussed.

The first post on Bulldozer design solutions is already up. It goes into some detail on how “the centerpiece of the “Bulldozer” module is its two tightly-linked processor cores” and explains how they will improve performance through parallel threading.

The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2.

Further details from the discussion go over Bulldozer’s new design for its floating point unit (FPU), and another Bulldozer Blog post gives some more information on what goes into these boxes.

According to AMD, “High performance computing relies heavily on vector (packed integer) and floating point operations, both handled in the FPU.  Bulldozer was designed to execute these operations at higher performance and using less power than the current generation of microprocessors.”

Less power usually means less heat, which is always good for overclockers. If those performance improvements are as strong as they sound, we’ve got a lot to look forward to. With enthusiasts everywhere just itching for more details on Bulldozer, this should go over well. While we still don’t have performance numbers to share, at least they’re trying to satiate us with plenty of technical details.

Read more about the first presentation in yesterday’s Bulldozer Blog post and be sure to watch the Bulldozer Blog itself this week for even more info.

– Jeremy Vaughan (hokiealumnus)