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Give credit where credit is due

There’s a lot of people out there who don’t have websites who have been the real pioneers in researching and exploring this. As I’ve said before, Armand Hirt got this ball rolling.
Go to forums in places like Ace’s Hardware, Ars Technica, Overclockers’ Workbench, and some others, and you have people experimenting, working on the best tools for cutting the bridges, figuring out
the circuit logic, and doing this well before some others claim credit for it without any acknowledgements.

Remember this, and give credit where credit is due.

For instance, John Carcich posted this. It describes the undocumented pins through which the
multiplier on the Duron/Thunderbird can be modified after the initial startup. (I’ll explain why this is important below.)

And this is someone named Hiroji who apparently has managed the feat on the AZ11. While the language is a big difficulty, this is the same
thing Anandtech tried to do a few days ago, and it looks like this person has succeeded, though exactly how isn’t clear at the moment.

What does all this mean?

Presuming no problems come up (i.e. CPU had an “unlocked multiplier”), what does this mean?

  1. It means that a motherboard can manipulate the multiplier over rated limits under some circumstances. Boards like the A7V and KT7 should work, provided AMD hasn’t taken additional measures (see below) to prevent it.
    Even boards that don’t have it as a feature (like the AZ11) could be cajoled into working, provided the circuitry on the board is left in place (as it was on the AZ11). It’s not clear whether he had to
    perform surgery on the chip, too, we need a few more details.

  2. We now know exactly what AMD would have to do to make it impossible for a motherboard to manipulate the multiplier; they’ll either have to remove or render inoperable (see below) these pins: AN27 AL27 AN25 AL25. If you look at
    a Duron or Thunderbird, and these pins are missing, then some CPU company is really serious about this. That doesn’t appear to stop CPU surgery, but we’ll have to see on that.

So this is a good sign, but we’re not out of the woods, yet. Don’t run out and buy a Duron/Thunderbird quite yet. There’s still more to be done until somebody can wrap this in a neat package and put a bow on it, but that
pretty much is what remains to be done. The core work has been done, just remember who got it done.

Update-7/16/00: Straight from an email from John Carcich:

Just a few minutes ago made another discovery re L1 bridges.

They are in “series” between those undocumented BP_FID pins and the BP_FID
signal busses…proved it by opening the L1 bridge connected to BPFID3.
Now AL25 formerly connected to signal busses no longer is, the pin is only
connected to “one end” of newly opened bridge. We have just clocked locked
BP_FID3!!! So the L1 bridges are the “clock lockers”…If AMD opens them
then the BP_FID interface “to mobos” via those 4 undocumented pins is
“gone”, have to work L3/L4 bridges or close the open L1s to work the pins.

So look for chips with any or all L1 bridges “open”…those will be the
ones “clock locked”. Should be simple to close them.

Ed. note: Yes, it would, just use a conductive pen to “connect the dots”.

This doesn’t mean there isn’t more to any lock than this; this will have to be further tested.

Email Ed


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