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ALL credit for this EXCELLENT article goes to FreeCableGuy at http://www.thetechrepository.com.
Adjusting [Advanced] Gunning Transceiver Logic (A/GTL+) Voltage Levels
for Increased Front Side Bus (FSB) Signaling Margins and Overclocking
Date: 17 January, 2007
Author: Kristopher Boughton
Introduction to A/GTL+ Signaling Conventions
Most Intel processor Front Side Bus (FSB) signals use [Advanced] Gunning Transceiver Logic (A/GTL+) signaling technology. GTL is a standard for electrical signals in CMOS circuits used to provide higher data transfer speeds with smaller voltage swings. (The GTL signal swings between 0.4v and 1.2v with a reference voltage of about 0.8v.) Only a small deviation of 0.4 volts (or thereabouts) from the reference voltage is required to switch between on and off states. Therefore, a GTL signal is said to be a low voltage swing logic signal. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Gunning Transceiver Logic has several advantages. The resistive termination of a GTL signal provides a clean signaling environment. Moreover, the low terminating voltage of 1.2 volts results in reduced voltage drops across the resistive elements. GTL has low power dissipation and can operate at high frequency and causes less electromagnetic interference (EMI) and signal line crosstalk than previous solutions.
Intel platforms implement a termination voltage level for GTL+ signals defined as VTT. Because these platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases as the voltage supplies are not coupled. Speed enhancements to data (4x) and address (2x) busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.
The A/GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 (low) or a logical 1 (high). GTLREF must be generated on the motherboard (usually derived from VTT by a passive voltage divider network). Termination resistors (RTT) for A/GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most A/GTL+ signals.
Current-generation Intel desktop processor I/O buffers work at a low nominal voltage of about 1.2v (VTT) - an essential element in the reduction of bus power. The bus includes a special automatic resistor compensation method to adjust the buffer strength dynamically during runtime. It accommodates the impacts of temperature, voltage drift, and bus topology (multiple processors and/or chipsets on a single bus). Thus, at any thermal and power state the processor bus has full impedance termination. As stated earlier, Intel processors and chipsets have split power planes that allow setting the I/O operating voltage (VTT) to an independent fixed value even though the CPU may be operating at a higher core voltage (VCC). As overclockers we can use this to our advantage.
Theory of Operation - Increasing Target Performance
VTT, sometimes referred to in the Basic Input/Output System (BIOS) as the FSB Termination Voltage, provides the low level signaling bias needed for the processors, chipsets, and all other devices on the bus to communicate. The FSB is the electrical interface that connects the processor to the chipset (also called the processor system bus or the system bus). All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
Intel rates the maximum VTT voltage for desktop processors at 1.55v (with respect to VSS). Because undershoot and overshoot specifications become more critical as the process technology for microprocessors shrink due to thinner gate oxide layers; we must note that violating these limits may excessively degrade the life expectancy of the processor and/or chipset. As such, it is important to recognize that any modification(s) that run processor(s) out of specification might results in damage that may not be warrantied by Intel. Don't let this scare you as this is just our standard disclaimer...
Note: Modifications to the circuit are shown in red.
Figure 1 is a simplified diagram illustrating standard bus topology. V(A) can represent any number of devices, such as a second processor die, as is the case with Kentsfield (but not Conroe), and in all cases, the chipset. (This should make sense as Cores 0/1 and Cores 2/3 must communicate via the FSB.) Figure 1 also models how VTT signals are terminated on-die.
Simply raising VTT may or may not create voltage margins necessary to sufficiently skew signals as required to meet minimum sample and hold times for increased bus frequencies. Additionally, processors are particularly sensitive to even small increases in VTT as bus impedances and termination resistance values are quite low. In fact, increasing VTT will most likely just create unwanted device heating with little to no change in FSB stabilization. The more focused approach lies in the tuning of each individual GTL reference level. Each die (note that Kentsfield has two dies) must be supplied with two separate GTL reference levels - one for the data bus and one for the address bus. This means that any board that supports Intel quad-core processors will require four adjustment potentiometers in order to modify all signal switching logic levels. Moreover, motherboards modified with a pair of potentiometers in order to support single-die tuning may not realize the full benefit of this modification when a dual-die processor is installed without first completing all modifications.
Data busses are much more sensitive to adjustments as these lines are consistently more heavily loaded than the address busses. Enterprising enthusiast who wishes to experiment would do much better to modify the data bus GTL reference voltage level(s) before any others. Figure 2 shows the relatively simple modification needed to begin adjusting levels - the potentiometer will allow setting the GTL reference level nearly anywhere from rail to rail (0.4v to 1.2v). Nominal GTL reference voltage for current generation processors/chipsets should be about 2/3 of VTT (or approximately 0.8v), although you may find your board's values a little lower (~0.75v).
[center [/center]
Figure 3 shows pad placement of the four (4) GTLREF signal used in the current-generation LGA775 socket platform. Take notice that this is a top-down view and that the image must be horizontally mirrored when viewing the CPU from the bottom. This image is provided so that those that wish to modify their motherboard may do so without the need for hardware specific instructions - by setting a multimeter to measure continuity and then probing these socket pins and components below the socket it is possible to locate modification points on just about any motherboard (circuit shown in Figure 2).
The capacitive nature of devices on the bus along with signal reflection and free wave propagation times lead to what is known as ringback (resonances on the bus as a results of quickly switching signals). Because of this, signals switching from a logical 0 to a logical 1 (and vice versa) do not always immediately and cleanly stabilize at their target pull-up or pull-down voltages. As a result, this ringback can cause either a processor or chipset pin sense voltage to unintentionally cross a GTLREF voltage threshold, creating a undesirable condition in which data corruption may occur, which can quickly manifest itself as instability or even system failure. Figure 4-1 and Figure 4-2 illustrate this point.
Once you begin adjusting GTLREF voltages (for each core data and address bus) you will find that different bus frequencies respond differently to variations in the voltage. This has to do with harmonics and reflected signals as the FSB changes. The best way to make adjustments is by using a "Clockgen" program from inside the OS to set a previously unstable FSB frequency while simultaneous moving the GTLREF voltage points. Memory or data intensive applications (such as Super PI) will stress the system the most. This inherent variation in system response and stability while passing through different ranges of FSB is most likely the reason that some users experience what they describes as "FSB holes." Just because the FSB signal timings are tuned for 350MHz and 450Mhz doesn't necessarily mean that they are adequate for 400Mhz FSB. Figure 5 illustrates this concept graphically.
The following, Figure 6, demonstrates why this modification is important. Without installing the biasing potentiometers vGTLref remains coupled to VTT making it impossible to adjust them independently. With the modification(s) installed the user has complete control over both VTT and vGTLref (an option that is actually included in the BIOS of the new DFI LANPARTY UT ICFX3200-T2R/G motherboard based on the AMD/ATI RD600 chipset!)
Practical Application - Motherboard Modifications
The following figure (Figure 7 shows all four (4) GTLREF signal modification points for the Intel D975XBX2 ("Bad Axe 2") motherboard as well as easy measurement points for both VTT and ground (VSS). The red x's represent the modification points (shown in the Figure 2 circuit above). The red 'lollipops' indicate an adjacent, electrically-connected pad - these can be extremely helpful when soldering to small SMT 0402 resistors such as those shown. Try bridging the tap connection point across the resistor edge to the nearby pad for added solder strength.
A nearby ground is also shown (any path connected should be as short as possible to minimize possible loop currents) as well as the tap point for VTT, which is used to adjust the default GTLREF signal level above it nominal value (if desired). All GTLREF voltages can be read directly from the modification point with reference to ground. Remember to refer to Figure 3 above for helpful information on determining which GTLREF signals should be modified and adjusted first.
***Refer to Figure 2 above for resistor values and circuit connection points.***
Although we can't show gains at this time we can safely say that it's due to lack of time. All of our time and energy for the last week has gone into building this article/guide. Come back often as we plan on adding more very soon!
References
Intel Corporation, Document Number: 315592-002 (January 2007):
Intel® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6000 Sequence Datasheet – on 65 nm Process in the 775-land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology
Intel Corporation, Document Number: 313079-001 (May 2006):
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Special thanks to Intel Corporation for providing the push in the right direction.
-FCG
Questions? Comments? Want to share what you know? Talk to us hereI hope this article helps explains the VTT and GTL relationship a little bit better. I know with the newer P35 boards, on some BIOSes, you can change the A/GTL voltage levels. This article helps explain why the 67% reference voltage seems to be a good starting point when you start overclocking. This guy is good!
Adjusting [Advanced] Gunning Transceiver Logic (A/GTL+) Voltage Levels
for Increased Front Side Bus (FSB) Signaling Margins and Overclocking
Date: 17 January, 2007
Author: Kristopher Boughton
Introduction to A/GTL+ Signaling Conventions
Most Intel processor Front Side Bus (FSB) signals use [Advanced] Gunning Transceiver Logic (A/GTL+) signaling technology. GTL is a standard for electrical signals in CMOS circuits used to provide higher data transfer speeds with smaller voltage swings. (The GTL signal swings between 0.4v and 1.2v with a reference voltage of about 0.8v.) Only a small deviation of 0.4 volts (or thereabouts) from the reference voltage is required to switch between on and off states. Therefore, a GTL signal is said to be a low voltage swing logic signal. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Gunning Transceiver Logic has several advantages. The resistive termination of a GTL signal provides a clean signaling environment. Moreover, the low terminating voltage of 1.2 volts results in reduced voltage drops across the resistive elements. GTL has low power dissipation and can operate at high frequency and causes less electromagnetic interference (EMI) and signal line crosstalk than previous solutions.
Intel platforms implement a termination voltage level for GTL+ signals defined as VTT. Because these platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases as the voltage supplies are not coupled. Speed enhancements to data (4x) and address (2x) busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.
The A/GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 (low) or a logical 1 (high). GTLREF must be generated on the motherboard (usually derived from VTT by a passive voltage divider network). Termination resistors (RTT) for A/GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most A/GTL+ signals.
Current-generation Intel desktop processor I/O buffers work at a low nominal voltage of about 1.2v (VTT) - an essential element in the reduction of bus power. The bus includes a special automatic resistor compensation method to adjust the buffer strength dynamically during runtime. It accommodates the impacts of temperature, voltage drift, and bus topology (multiple processors and/or chipsets on a single bus). Thus, at any thermal and power state the processor bus has full impedance termination. As stated earlier, Intel processors and chipsets have split power planes that allow setting the I/O operating voltage (VTT) to an independent fixed value even though the CPU may be operating at a higher core voltage (VCC). As overclockers we can use this to our advantage.
Theory of Operation - Increasing Target Performance
VTT, sometimes referred to in the Basic Input/Output System (BIOS) as the FSB Termination Voltage, provides the low level signaling bias needed for the processors, chipsets, and all other devices on the bus to communicate. The FSB is the electrical interface that connects the processor to the chipset (also called the processor system bus or the system bus). All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
Intel rates the maximum VTT voltage for desktop processors at 1.55v (with respect to VSS). Because undershoot and overshoot specifications become more critical as the process technology for microprocessors shrink due to thinner gate oxide layers; we must note that violating these limits may excessively degrade the life expectancy of the processor and/or chipset. As such, it is important to recognize that any modification(s) that run processor(s) out of specification might results in damage that may not be warrantied by Intel. Don't let this scare you as this is just our standard disclaimer...
Note: Modifications to the circuit are shown in red.
Figure 1 is a simplified diagram illustrating standard bus topology. V(A) can represent any number of devices, such as a second processor die, as is the case with Kentsfield (but not Conroe), and in all cases, the chipset. (This should make sense as Cores 0/1 and Cores 2/3 must communicate via the FSB.) Figure 1 also models how VTT signals are terminated on-die.
Simply raising VTT may or may not create voltage margins necessary to sufficiently skew signals as required to meet minimum sample and hold times for increased bus frequencies. Additionally, processors are particularly sensitive to even small increases in VTT as bus impedances and termination resistance values are quite low. In fact, increasing VTT will most likely just create unwanted device heating with little to no change in FSB stabilization. The more focused approach lies in the tuning of each individual GTL reference level. Each die (note that Kentsfield has two dies) must be supplied with two separate GTL reference levels - one for the data bus and one for the address bus. This means that any board that supports Intel quad-core processors will require four adjustment potentiometers in order to modify all signal switching logic levels. Moreover, motherboards modified with a pair of potentiometers in order to support single-die tuning may not realize the full benefit of this modification when a dual-die processor is installed without first completing all modifications.
Data busses are much more sensitive to adjustments as these lines are consistently more heavily loaded than the address busses. Enterprising enthusiast who wishes to experiment would do much better to modify the data bus GTL reference voltage level(s) before any others. Figure 2 shows the relatively simple modification needed to begin adjusting levels - the potentiometer will allow setting the GTL reference level nearly anywhere from rail to rail (0.4v to 1.2v). Nominal GTL reference voltage for current generation processors/chipsets should be about 2/3 of VTT (or approximately 0.8v), although you may find your board's values a little lower (~0.75v).
[center [/center]
Figure 3 shows pad placement of the four (4) GTLREF signal used in the current-generation LGA775 socket platform. Take notice that this is a top-down view and that the image must be horizontally mirrored when viewing the CPU from the bottom. This image is provided so that those that wish to modify their motherboard may do so without the need for hardware specific instructions - by setting a multimeter to measure continuity and then probing these socket pins and components below the socket it is possible to locate modification points on just about any motherboard (circuit shown in Figure 2).
The capacitive nature of devices on the bus along with signal reflection and free wave propagation times lead to what is known as ringback (resonances on the bus as a results of quickly switching signals). Because of this, signals switching from a logical 0 to a logical 1 (and vice versa) do not always immediately and cleanly stabilize at their target pull-up or pull-down voltages. As a result, this ringback can cause either a processor or chipset pin sense voltage to unintentionally cross a GTLREF voltage threshold, creating a undesirable condition in which data corruption may occur, which can quickly manifest itself as instability or even system failure. Figure 4-1 and Figure 4-2 illustrate this point.
Once you begin adjusting GTLREF voltages (for each core data and address bus) you will find that different bus frequencies respond differently to variations in the voltage. This has to do with harmonics and reflected signals as the FSB changes. The best way to make adjustments is by using a "Clockgen" program from inside the OS to set a previously unstable FSB frequency while simultaneous moving the GTLREF voltage points. Memory or data intensive applications (such as Super PI) will stress the system the most. This inherent variation in system response and stability while passing through different ranges of FSB is most likely the reason that some users experience what they describes as "FSB holes." Just because the FSB signal timings are tuned for 350MHz and 450Mhz doesn't necessarily mean that they are adequate for 400Mhz FSB. Figure 5 illustrates this concept graphically.
The following, Figure 6, demonstrates why this modification is important. Without installing the biasing potentiometers vGTLref remains coupled to VTT making it impossible to adjust them independently. With the modification(s) installed the user has complete control over both VTT and vGTLref (an option that is actually included in the BIOS of the new DFI LANPARTY UT ICFX3200-T2R/G motherboard based on the AMD/ATI RD600 chipset!)
Practical Application - Motherboard Modifications
The following figure (Figure 7 shows all four (4) GTLREF signal modification points for the Intel D975XBX2 ("Bad Axe 2") motherboard as well as easy measurement points for both VTT and ground (VSS). The red x's represent the modification points (shown in the Figure 2 circuit above). The red 'lollipops' indicate an adjacent, electrically-connected pad - these can be extremely helpful when soldering to small SMT 0402 resistors such as those shown. Try bridging the tap connection point across the resistor edge to the nearby pad for added solder strength.
A nearby ground is also shown (any path connected should be as short as possible to minimize possible loop currents) as well as the tap point for VTT, which is used to adjust the default GTLREF signal level above it nominal value (if desired). All GTLREF voltages can be read directly from the modification point with reference to ground. Remember to refer to Figure 3 above for helpful information on determining which GTLREF signals should be modified and adjusted first.
***Refer to Figure 2 above for resistor values and circuit connection points.***
Although we can't show gains at this time we can safely say that it's due to lack of time. All of our time and energy for the last week has gone into building this article/guide. Come back often as we plan on adding more very soon!
References
Intel Corporation, Document Number: 315592-002 (January 2007):
Intel® Core™2 Extreme Quad-Core Processor QX6700 and Intel® Core™2 Quad Processor Q6000 Sequence Datasheet – on 65 nm Process in the 775-land LGA Package supporting Intel® 64 architecture and Intel® Virtualization Technology
Intel Corporation, Document Number: 313079-001 (May 2006):
Dual-Core Intel® Xeon® Processor 5000 Series Datasheet
Special thanks to Intel Corporation for providing the push in the right direction.
-FCG
Questions? Comments? Want to share what you know? Talk to us hereI hope this article helps explains the VTT and GTL relationship a little bit better. I know with the newer P35 boards, on some BIOSes, you can change the A/GTL voltage levels. This article helps explain why the 67% reference voltage seems to be a good starting point when you start overclocking. This guy is good!
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