AMA about IC design, semiconductors, etc.

[]-[itman]

Hi All,

I first joined this forum in 2001 as a teenager who was really getting into computers, overclocking, PC gaming, etc. I found this site initially because of the overclocking database that used to be on the front page. If you weren't around back then, this site used to maintain a database of self-reported overclocks from users who would list their CPU, stepping (something that was important back then), max frequency, and I believe voltage. IIRC, they had a field for additional notes as well (MB, RAM, etc.). Anyway, it was my dream back then not only to build computers, but design the chips inside of them. I won't bore you with my entire life's story, but after some delays in getting through college due to some big life events, I graduated with a Master of Science degree in Electrical Engineering and have been working in the semiconductor industry for roughly a decade.

I originally thought I was going to go into digital design and work for AMD, or Intel, or similar, but after speaking with multiple professors my senior year, I decided to go into high frequency (RF - mmWave) IC design. I say this so that you know where my knowledge is strong and where it is lacking. To be more specific, if you have high frequency design questions, I'll be gladly to answer them. If you have analog design questions, I can probably answer them. If you have digital design questions, I can answer some of them, especially if it is the basics of digital design. As you work your way up from the gate level (where I feel pretty confident) to architectural questions, my knowledge base gets weaker and weaker. I also have experience in multi-die packages (so things like chiplets/tiles just in a different context), so I can probably answer those types of questions too.

So, with the intro out of the way, I just thought I'd offer a chance to anyone that may have a burning question about how semiconductors work, or why things are done a certain way, or where things are headed in the industry, or questions about getting into the industry, to ask a question and I will do my very best to answer and hope that others can find value in this thread. The last caveat I will state is that I am working full time with a family, so please be patient as I find the time to answer questions. Lastly, I will try to stick to conceptual answers, rather than going through formulas and math, and will post visual aids if I can find good ones through a quick google search as I don't have the skill or time to draw them myself. With all that said, feel free to AMA.

 

[Flamethrower1972]

Do they still use logic testers anymore?

 

[mackerel]

Background: I have a bachelor degree in electronic engineering, but my working life was spent in electro-acoustics so not terribly useful for the likes of CPU/GPU talk. My idea of "high frequency" is around 20 kHz

For clocked digital designs, what is the power scaling with voltage? To expand on that, if we had something that follows ohms law, we just need to know the resistance of it. But switching transistors quickly in a semiconductor probably isn't simply resistive? I think I've seen Intel talk about capacitance in this context with Lunar Lake. Or is there some semiconductor voltage non-linearity to consider?

 

[]-[itman]

Background: I have a bachelor degree in electronic engineering, but my working life was spent in electro-acoustics so not terribly useful for the likes of CPU/GPU talk. My idea of "high frequency" is around 20 kHz

For clocked digital designs, what is the power scaling with voltage? To expand on that, if we had something that follows ohms law, we just need to know the resistance of it. But switching transistors quickly in a semiconductor probably isn't simply resistive? I think I've seen Intel talk about capacitance in this context with Lunar Lake. Or is there some semiconductor voltage non-linearity to consider?

For clocked digital designs, there are 2 powers to consider, static and dynamic. The static power should look familiar to you, it is Pstatic = I*V, where V is the supply voltage and I is the leakage current (MOSFETs still allow a small amount of current when off). The dynamic power isn't as straight forward, but it boils down to Pdynamic = C*F*V^2 where V is the supply voltage, F is the frequency, and C is the load capacitance. When I say load capacitance, I am referring to the input capacitance of one stage that the previous stage must charge/discharge (all added up if talking about the total design).

Traditionally, static power was pretty much ignored as the leakage of older processes was very small, but as things shrunk down, the leakage currents increased and additional techniques were needed to keep the leakage currents down with newer processes. So, while static power can't be fully ignored, dynamic power still dominates the power consumption and so, to answer your question with a simplified view, the power consumption increases by the square of the voltage. In other words, if you doubled the supply voltage (not realistic but just as an example) and nothing else changed, your power would increase by 4 times.

In the real world, it's a bit more complicated as temperature plays a significant role in all this as well, but as a good estimate, power increases with voltage squared is what you can go with.

Hope this answers your question!

 

[]-[itman]

Do they still use logic testers anymore?

You'll have to be more specific as there's lots of different types of logic testers

In a general sense, yes, logic testers/analyzers are still used.

 

[mackerel]

it boils down to Pdynamic = C*F*V^2

Thanks. It was the voltage term I wasn't very sure of. Intuitively there is a frequency component. If it were a resistive load, then V^2 was obvious, but then I think about the non-linear voltage characteristics of a PN junction and... looking back I guess that's where I went off track. If we're using it for switching, then at a high level it doesn't matter.

Is that capacitance a physical value or is it an effective value for this purpose?

Good point about the static losses. That wasn't part of my original intent.

In the real world, it's a bit more complicated as temperature plays a significant role in all this as well, but as a good estimate, power increases with voltage squared is what you can go with.

Long term overclockers, especially those who dabble with more exotic cooling, are familiar with temperature effects. At least at an observational level. My most fun OC was a 280X. If it wasn't for built in limits that was on the edge of thermal runaway at stock.

 

[]-[itman]

Is that capacitance a physical value or is it an effective value for this purpose?

I'm not sure what you are asking. Can you elaborate?

 

[mackerel]

Guess I'm over-thinking things again. It doesn't really matter, but when I said physical, I mean that as a real capacitance you could isolate and measure. When I say effective, that would be an equivalent capacitance at typical conditions, possibly taking into account other factors and non-linearities with frequency.

 

[]-[itman]

Guess I'm over-thinking things again. It doesn't really matter, but when I said physical, I mean that as a real capacitance you could isolate and measure. When I say effective, that would be an equivalent capacitance at typical conditions, possibly taking into account other factors and non-linearities with frequency.

Ok, I think I understand what you are asking. So, for purposes of scaling, you would ignore the C term as it is assumed to be constant between frequency and voltage adjustments. In terms of absolute calculations, you can calculate a theoretical value for C, but in the real world, there are multiple things that will cause that value to shift. Additionally, for an actual design, there are way too many logic gates to calculate them each individually, even if just using the ideal estimate. Design tools do estimate this capacitance as part of the design flow, but it's not super accurate once you go full chip scale. Pre-silicon power estimates are typically one of the most inaccurate parts of CPU design for this, as well as other reasons. So, you don't really know with good accuracy what your power profile is going to look like until you test the silicon. Not that you won't have any idea, it's just one of the hardest things to get close to accurate.

Let me know if this helps or if you were asking something else.

 

[AJL]

For clocked digital designs, there are 2 powers to consider, static and dynamic. The static power should look familiar to you, it is Pstatic = I*V, where V is the supply voltage and I is the leakage current (MOSFETs still allow a small amount of current when off). The dynamic power isn't as straight forward, but it boils down to Pdynamic = C*F*V^2 where V is the supply voltage, F is the frequency, and C is the load capacitance. When I say load capacitance, I am referring to the input capacitance of one stage that the previous stage must charge/discharge (all added up if talking about the total design).

Yup, or, from an old text book:



That sort of stuff certainly cooks my noggin
Got it from ATF member I knew years ago (semicon process developer).