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AMD Bulldozer breaks world speed
- Thread starter WhitehawkEQ
- Start date
- Joined
- Nov 12, 2002
- Location
- Rootstown, OH
We recently changed contacts at AMD, so I'm not sure if I should expect a response or when - the last guy was very good, hopefully the newbies are good also.
![]-[itman](/forums/data/avatars/m/9/9309.jpg?1650325391){kind=avatar}
SSE operands are floating point and are 128 bits wide. AVX, intel's new instruction set, is 256 bits wide as seen here, http://www.anandtech.com/show/3922/intels-sandy-bridge-architecture-exposed/3 . This is different from the precision of the actual floating point numbers which Chasr pointed out are 32 or 64 bit, although this is really only limited by the register width which can be overcome if deemed necessary though never really is.
As far as simultaneous execution, it's not in the width of the units but in how many units each core actually has. As a basic hypothetical, if cpu A has 3 64-bit ALU's (integer) and cpu B has 2 128-bit ALU's, Assuming all you need are 64-bit operands and all else is equal, cpu A will be able to process 50% more integer operations than cpu B. It is possible to break up cpu B's 2 128-bit ALU's to allow for more than 1 operation in the ALU, but this would probably cause more problems than fix them.
Really, per clock cycle an ALU can only perform 1 instruction at whatever width (bit range) it is built. There are a lot of tricks and modern circuit design that actually allow for greater efficiency than this, but in general, all else being equal, the cpu with more ALU's will be faster for integer calculations assuming 128-bit is unneeded.
Sorry, I didn't mean to go on and on about this and really, there's so much from branch prediction, to miss penalties, to cache hierchy, and much more that goes into this that unless you are intimately familiar with the bulldozer architecture, we won't know for sure how well it performs until we bench it. I also do not follow the actual instruction sets used by Stanford for F@H, so as far as folding performance, I will say I'm in the dark, but I am excited to see if we have a lower cost (and maybe lower power) alternative for helping the cause.
Btw, I know most of you probably don't know me, but I've been around a while, mostly lurking for a few years now. I really don't have any resources for F@H currently (see sig) but I have sporadic contributions once in a while and root you guys on in spirit. One day I'll be back to fold with a vengeance
As far as simultaneous execution, it's not in the width of the units but in how many units each core actually has. As a basic hypothetical, if cpu A has 3 64-bit ALU's (integer) and cpu B has 2 128-bit ALU's, Assuming all you need are 64-bit operands and all else is equal, cpu A will be able to process 50% more integer operations than cpu B. It is possible to break up cpu B's 2 128-bit ALU's to allow for more than 1 operation in the ALU, but this would probably cause more problems than fix them.
Really, per clock cycle an ALU can only perform 1 instruction at whatever width (bit range) it is built. There are a lot of tricks and modern circuit design that actually allow for greater efficiency than this, but in general, all else being equal, the cpu with more ALU's will be faster for integer calculations assuming 128-bit is unneeded.
Sorry, I didn't mean to go on and on about this and really, there's so much from branch prediction, to miss penalties, to cache hierchy, and much more that goes into this that unless you are intimately familiar with the bulldozer architecture, we won't know for sure how well it performs until we bench it. I also do not follow the actual instruction sets used by Stanford for F@H, so as far as folding performance, I will say I'm in the dark, but I am excited to see if we have a lower cost (and maybe lower power) alternative for helping the cause.
Btw, I know most of you probably don't know me, but I've been around a while, mostly lurking for a few years now. I really don't have any resources for F@H currently (see sig) but I have sporadic contributions once in a while and root you guys on in spirit. One day I'll be back to fold with a vengeance
- Joined
- Feb 5, 2008
- Location
- Houston, TX
Btw, I know most of you probably don't know me, but I've been around a while, mostly lurking for a few years now. I really don't have any resources for F@H currently (see sig) but I have sporadic contributions once in a while and root you guys on in spirit. One day I'll be back to fold with a vengeance
Hopefully Zambezi will fold well and give you an affordable option to build a PC with. We should know in about 1 month
- Joined
- Mar 15, 2005
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- Valley of the Sun
SSE operands is the key factor there. The chip that can do the most SSE operands per clock cycle (or cycles) will be the performance winner in FAH. Not core counts, or partial core counts, or FPU counts, or thread counts, or GHz, none of it. SSE opperands per clock cycle is the primary factor to consider.
A previous discussion of this topic seemed to conclude that the new Intel chips could not sandwich 2x128 in to 1 256 bit instruction unless the program code supported AVX. And FAH won't support AVX in the fahcores for a little while yet. However, AMD was going to supliment it's chip design to enable 2x128 in to 1 256 bit instruction without the need of AVX code support. AMD was going to support this natively. This potentially makes the AMD chip design 2x as fast (theoretical max) running fah (at least until fah supported AVX, and then they'd both be back on about even ground again).
Standard disclaimer! This is all conjecture based on prereleased marketing data. No one is 100% sure what features have and have not made their way in to the released products yet, so tons of grains of salt still required. And very anxious to see ACTUAL performance results.
A previous discussion of this topic seemed to conclude that the new Intel chips could not sandwich 2x128 in to 1 256 bit instruction unless the program code supported AVX. And FAH won't support AVX in the fahcores for a little while yet. However, AMD was going to supliment it's chip design to enable 2x128 in to 1 256 bit instruction without the need of AVX code support. AMD was going to support this natively. This potentially makes the AMD chip design 2x as fast (theoretical max) running fah (at least until fah supported AVX, and then they'd both be back on about even ground again).
Standard disclaimer! This is all conjecture based on prereleased marketing data. No one is 100% sure what features have and have not made their way in to the released products yet, so tons of grains of salt still required. And very anxious to see ACTUAL performance results.
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- High Desert, Calif.
hehe, daddy wants a new chip! 
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- Location
- Sierra Vista, AZ
Apparently AMD is having some major yield problems. Does not bold well for BD.
http://www.anandtech.com/show/4894/amd-confirms-32nm-yield-issues-at-global-foundries
At this rate SB-E may come out before BD.
http://www.anandtech.com/show/4894/amd-confirms-32nm-yield-issues-at-global-foundries
At this rate SB-E may come out before BD.
- Joined
- Oct 14, 2007
Anand inserted the BD comment in there. AMD's statement was only concerning Llano. FWIW.
- Joined
- Nov 12, 2002
- Location
- Rootstown, OH
Nope. It isn't pushing back the BD release, and SB-E has not had any talk of coming out soon. Bad yields may impact availability, but more likely it will just affect AMD revenue - bad yields mean lower profit margins on the chips.
Mostly, the statements point to the past about yields - hopefully that isn't true for the future. The news about Bergman is probably more alarming however than this news about yields.
Mostly, the statements point to the past about yields - hopefully that isn't true for the future. The news about Bergman is probably more alarming however than this news about yields.
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- Folding@Home
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- Mirabel, Quebec, Canada
AMD's first eight-core desktop processors detailed
http://www.computerworld.com/s/article/9220590/AMD_s_first_eight_core_desktop_processors_detailed
http://www.computerworld.com/s/article/9220590/AMD_s_first_eight_core_desktop_processors_detailed
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- Folding@Home
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- Jul 5, 2008
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- CFL
Damn. Had high hopes for AMD Bulldozer...
preliminary reviews show it to perform poorly compared to 2600K i7...
http://pcper.com/reviews/Processors...ulldozer-Unearth-AMD-Victory/Closing-Thoughts
http://www.anandtech.com/show/4955/the-bulldozer-review-amd-fx8150-tested/8
preliminary reviews show it to perform poorly compared to 2600K i7...
http://pcper.com/reviews/Processors...ulldozer-Unearth-AMD-Victory/Closing-Thoughts
http://www.anandtech.com/show/4955/the-bulldozer-review-amd-fx8150-tested/8
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- Jul 5, 2008
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- CFL
Well I just read the first few posts of our review.... don't know what to make of it compared to SB 2600Ks..
From our own Front page:
Floating point performance isn’t looking so good. Not that it’s bad compared to the professed competition, but that they actually lost ground to the Thuban. I mentioned this might happen based on the sharing of FPU cores rather than duplicating the entire core, which would have given the chip a healthy boost with eight FPU cores instead of four. It seems those fears have been realized and the Thuban – with six FPU cores – out-performs Bulldozer. For better or worse, AMD has put all their performance eggs on the CPU side of their chip.
That does not bode well for Folding@home performance.
Floating point performance isn’t looking so good. Not that it’s bad compared to the professed competition, but that they actually lost ground to the Thuban. I mentioned this might happen based on the sharing of FPU cores rather than duplicating the entire core, which would have given the chip a healthy boost with eight FPU cores instead of four. It seems those fears have been realized and the Thuban – with six FPU cores – out-performs Bulldozer. For better or worse, AMD has put all their performance eggs on the CPU side of their chip.
That does not bode well for Folding@home performance.
Thanks to Hokie we have some initial FaH benchmarks,
I think with the performance and the power a 2600k is a much better investment for folding no?
I had promised folding results to Shelnutt2, but they couldn't make the review. So, they will be posted in the first post!
Regular SMP work unit - 13698.9ppd
Bigadv work unit - 13859.2ppd
So between 13,500 and 14,000 at stock, which is right where it's positioned - around the PPD of a 2500K.
I think with the performance and the power a 2600k is a much better investment for folding no?
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- Oct 14, 2007
As a folding farm cpu, the Bulldozer is more like a lawn tractor that guzzles 30 gal of diesel per hour. As a guy that started out as an AMD fanboy, I'm sorely disappointed in it's folding performance, but on the other hand, I'm glad it didn't make my current hardware obsolete, like SB and the QRB did.
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