• Welcome to Overclockers Forums! Join us to reply in threads, receive reduced ads, and to customize your site experience!

AMD going 20nm this year?

Overclockers is supported by our readers. When you click a link to make a purchase, we may earn a commission. Learn More.
Different arch, but I get your point. I am not a CE so I can't define it for you. As a consumer I can say this.

If reducing die size was unprofitable why would either company pursue it?

I didn't say it was "unprofitable" what I said was the profits are shrinking per chip and will continue to do so without new innovations. Intel is using the "tri-gate" to try and move in that new direction however as most people are seeing there are inherent problems with that. Just moving to 22nm from 32nm means that "leakage" becomes an increasing problem (thinner layers between traces creates greater leakage potential). Intel atm is experiencing problems with the sidewall doping on the "FinFET's" which more than likely is the cause of the temperature problems (due to leakage IMHO) everyone is seeing in most (there are some "golden" IB's) of the IB chips produced which will hopefully be solved as the process matures. The "stacked die" is supposed to be one of the ways that their moving to in order to solve some of those problems but we'll see how that pans out.

Here's an article about FinFET and the challenges -

http://cosmos886to.blogspot.com/2011/05/intels-tri-gate-finfets-lead-tsmc-skips.html

Hu said the fin must be very thin, about equal to the gate length, in order to accomplish the goal of suppressing the leakage current. To keep the fin thickness exactly the same across the wafer requires that the process be very well controlled.

I.E. Higher chance of failure.
 
Last edited:
Some time things get more expensive for the sake of saving battery power, wall power and increasing performance, shrinking transistors increases there speed.

It's just getting more expensive and the companies are grasping at straws

The choice for AMD is planar transistor or FinFET transistor and FinFET is intels other 3D idea.

Almost thanked you there. Does it decrease power consumption or increase speed? Current Haswell projections are 120-160W Something supposed to be released soon on Intels roadmap. Something announced to use 1/20th the power at same performance of current gen.

Look I am not saying Intel is a great big meany. they are, I don't care, so is Microsoft. What is the alternative Apple products? LOL

Ok I finished laughing. Now on to serious business.

As mentioned before, if it is not fiscally responsible if a company produce can it? If Intel is intent on pushing trigate into 14nm, it wont be desktop. It is not possible to do that and maintain current specs of performance. Even with a skewed scale of performance. Not in one year. How will they cool it? They going to change that community not controlled by them as well? Or leave it to LN2 guys to carry their credulity into the 201X years?

Oh oh oh I got it. heatpipes within the cpu. to transfer heat to a larger IHS. Think its going to happen? me neither.
 
Almost thanked you there. Does it decrease power consumption or increase speed? Current Haswell projections are 120-160W Something supposed to be released soon on Intels roadmap. Something announced to use 1/20th the power at same performance of current gen.

Look I am not saying Intel is a great big meany. they are, I don't care, so is Microsoft. What is the alternative Apple products? LOL

Ok I finished laughing. Now on to serious business.

As mentioned before, if it is not fiscally responsible if a company produce can it? If Intel is intent on pushing trigate into 14nm, it wont be desktop. It is not possible to do that and maintain current specs of performance. Even with a skewed scale of performance. Not in one year. How will they cool it? They going to change that community not controlled by them as well? Or leave it to LN2 guys to carry their credulity into the 201X years?

You're assuming that the profit margin on 45nm 32nm was not very high. I'll have to find the info on it but I believe it was somewhere around 64% for intel.

Still looking but here's the xeon stat for '09 http://www.investorplace.com/2010/07/intel-itc-faces-choice-market-share-or-profit-margins/

Intel’s server processor profit margins were 50% in 2009, versus 10% for AMD.

Intel's Atom - http://www.engadget.com/2008/03/30/atom-processor-to-cost-intel-just-6-to-8/

AMD's Desktop profit margin according to Trefis is about 16% now (look at the first graph chart) - http://www.thestreet.com/story/10943082/1/amd-profit-margins-critical-to-price-estimate.html

Intel's total desktop CPU margin EBITD 54.9% (averaged from all desktop cpu's from intel) http://www.trefis.com/company?hm=INTC.trefis#/INTC/n-0010/0053?from=rhs&c=top
 
Last edited:
Some time things get more expensive for the sake of saving battery power, wall power and increasing performance, shrinking transistors increases there speed.

It's just getting more expensive and the companies are grasping at straws

The choice for AMD is planar transistor or FinFET transistor and FinFET is intels other 3D idea.

Almost thanked you there. Does it decrease power consumption or increase speed? Current Haswell projections are 120-160W Something supposed to be released soon on Intels roadmap. Something announced to use 1/20th the power at same performance of current gen.

Look I am not saying Intel is a great big meany. they are, I don't care, so is Microsoft. What is the alternative Apple products? LOL

Ok I finished laughing. Now on to serious business.

As mentioned before, if it is not fiscally responsible if a company produce can it? If Intel is intent on pushing trigate into 14nm, it wont be desktop. It is not possible to do that and maintain current specs of performance. Even with a skewed scale of performance. Not in one year. How will they cool it? They going to change that community not controlled by them as well? Or leave it to LN2 guys to carry their credulity into the 201X years?

Oh oh oh I got it. heatpipes within the cpu. to transfer heat to a larger IHS. Think its going to happen? me neither.

Intel did increase the cpu speed with IB and it's doing fine at stock speeds. They push the limits and AMD is going to do the same maybe at 20-14nm AMD is going to run cooler with Depleted SOI planar transistor.

However intel is doing the Tri-gate for 10nm and less for the future that's there reasoning, will it work i don't know, they have failed before.

like i said before It's just getting more expensive and the companies are grasping at straws and there is a ending point to shrinking transistors.
 
You're assuming that the profit margin on 45nm 32nm was not very high. I'll have to find the info on it but I believe it was somewhere around 64% for intel.

NO 64% wtf.. why do you disagree with me then. EDIT: without know anything I said 75% minus increase in material cost... dont keep proving my points for me.

Everyone is assuming that as the process size shrinks each wafer cost is the same or only a little more and since more chips are on the wafer that means cost goes down. The fallacy in that is the assumption the wafer costs are the same. Actually wafer costs rise significantly as the process goes down. I'm trying to dig up the presentation by if I remember correctly NVidia discussing the problems with die shrinks and reduced profits per chip.

Edit -

http://www.techdesignforums.com/eda/technique/computational-scaling-implications-for-design/

I said that 45nm to 32nm almost doubled number of chips. Dont have the skill to know 32nm to 20nm so cant apply it. You can scroll back for the things I said DO increase cost. well hell 1995 to 2000 stuff increases in cost. lol:blah:


Enjoyed the intelligent discussion. Missed old what's his name "I knew him well"

tyranus something. Great dude that actually worked in a fab.
 
Last edited:
NO



I said that 45nm to 32nm almost doubled number of chips. Dont have the skill to know 32nm to 20nm so cant apply it. You can scroll back for the things I said DO increase cost. well hell 1995 to 2000 stuff increases in cost. lol:blah:


Enjoyed the intelligent discussion. Missed old what's his name "I knew him well"

tyranus something. Great dude that actually worked in a fab.

You're making multiple assumptions here. First going 45nm to 32nm didn't "nearly double" the amount of chips per wafer. Second you're assuming that when moving from the 45nm node to the 32nm node that the processor transistor count stayed the same. And most importantly you're also assuming that the yield per wafer stayed the same going from 45nm to 32nm. Even with all of that it still ignores the fact that as the advanced nodes hit 28nm and below the complexities and problems skyrocketed (and therefore costs increased). If the # of CPU's yielded per wafer had stayed the same going from SB to IB you would be seeing a huge increase in price. The only saving grace was that because it shrunk to 22nm the # of CPU's yielded is "supposed" to increase (although with the fab problems they're having I would love to see if that's really the case).

As for the profit margins. What I am saying is that Intel is in a much better position to absorb a decrease in profit margins by shifting to 22nm than companies like AMD. The single worst decision that came out of AMD in the last decade *cough* Hector Ruiz *cough* was spinning off the fabrication facilities into Global Foundries. Now AMD has to rely on a 3rd party to manufacture their dies who are factoring in a profit before AMD even gets their hands on the dies. No surprise that with all of that in mind they're at 45nm moving to 32nm with Piledriver.
 
Last edited:
I said that 45nm to 32nm almost doubled number of chips. Dont have the skill to know 32nm to 20nm so cant apply it.:
Your not thinking correctly when they shrink transistors they add more transistors that's the hole point from the beginning, power saving and speed was a extra in time. Have you seen the size of the SB die or BD.

They have increased the size of the wafers to try and lower cost however they have problems there also.
 
Last edited:
Hmm, perhaps not however I wouldn't be surprised if nano tubes get used in the manner you described regarding heat pipes.
 
You're making multiple assumptions here. First going 45nm to 32nm didn't "nearly double" the amount of chips per wafer. Second you're assuming that when moving from the 45nm node to the 32nm node that the processor transistor count stayed the same. And most importantly you're also assuming that the yield per wafer stayed the same going from 45nm to 32nm. Even with all of that it still ignores the fact that as the advanced nodes hit 28nm and below the complexities and problems skyrocketed (and therefore costs increased). If the # of CPU's yielded per wafer had stayed the same going from SB to IB you would be seeing a huge increase in price. The only saving grace was that because it shrunk to 22nm the # of CPU's yielded is "supposed" to increase (although with the fab problems they're having I would love to see if that's really the case).

As for the profit margins. What I am saying is that Intel is in a much better position to absorb a decrease in profit margins by shifting to 22nm than companies like AMD. The single worst decision that came out of AMD in the last decade *cough* Hector Ruiz *cough* was spinning off the fabrication facilities into Global Foundries. Now AMD has to rely on a 3rd party to manufacture their dies who are factoring in a profit before AMD even gets their hands on the dies. No surprise that with all of that in mind they're at 45nm moving to 32nm with Piledriver.

First I will addres your dual points that cover 4 areas. Counting is not your strong suit.

1) math shows yes I am right
2) yield values which you bring up are another argument, not as large an issue elsewhere not an issue here.
3) I never assumed the transistor count stayed the same, who told you that I will punch them in the eyehole.
4) "The only saving grace was that because it shrunk to 22nm the # of CPU's yielded is "supposed" to increase" Do you have some information otherwise except some stupid "news" post and a familiarity with nvidias incapability to produce a solid 45nm product on TSMC foundry?
A1) Math shows that 32nm produces nearly double the amount of 45nm chips.
A2) never said transistor count stayed the same. WTF you talking about.
A3) By eyehole I mean something worse and by punch I mean not using any part of my body eww. Defintiley don't want my fist in anyones buttocks.
A4) Per Anything, sorry that is just a ridiculous assumption. Come one. I asked their PR firm about some SSD facts, things knownw on the internet and got called and insider. whatever the **** that means. Dunno, I dont Intel.


A5) to the question you didnt ask. Yes it is cheaper to produce a smaller size than continue to produce the ame thing repeatedly.



Your not thinking correctly when they shrink transistors they add more transistors that's the hole point from the beginning, power saving speed was a extra in time. Have you seen the size of the SB die or BD.

They have increased the size of the wafers to try and lower cost however they have problems there also.

You are thinking wrong. Adding transistors has nothing to do with physically adding anything. It is a design etched in acid. Believe it or not, you have no choice on whether it is a cpu or not. Just like you have no choice but to be wrong, because you are. IT isa lithography process and designed before you entered the equation.

EDIT: Got caught up in the "fury" of posting. sorry. the posts are ridiculous no denying that. My responses are uncalled for I apologize. Not deleting them cuz they are funny. If you dont find them funny, report them and me. I will snicker the whole time :)
 
Last edited:
Hmm, perhaps not however I wouldn't be surprised if nano tubes get used in the manner you described regarding heat pipes.

That's one of the things they're looking at, "graphene" to replace the standard materials. There was another one that showed better promise than graphene but I can't think of what it is off the top of my head.
 
Your not thinking correctly when they shrink transistors they add more transistors that's the hole point from the beginning, power saving and speed was a extra in time. Have you seen the size of the SB die or BD.

They have increased the size of the wafers to try and lower cost however they have problems there also.

You are thinking wrong. Adding transistors has nothing to do with physically adding anything. It is a design etched in acid. Believe it or not, you have no choice on whether it is a cpu or not. Just like you have no choice but to be wrong, because you are. IT isa lithography process and designed before you entered the equation.

You are off the tracks, i'm done.
 
You are off the tracks, i'm done.


am I? Anyway good hanging with you.

EDIT: Oh i get it.. was supposed to be DECREASED not increased. nice typo catch ;)

EDIT EDIT: BTW If I offended your sensibilities I apologize for that. Was trying to discourse and might have gone too far in certain ascertations.
 
Last edited:
First I will addres your dual points that cover 4 areas. Counting is not your strong suit.

1) math shows yes I am right
2) yield values which you bring up are another argument, not as large an issue elsewhere not an issue here.
3) I never assumed the transistor count stayed the same, who told you that I will punch them in the eyehole.
4) "The only saving grace was that because it shrunk to 22nm the # of CPU's yielded is "supposed" to increase" Do you have some information otherwise except some stupid "news" post and a familiarity with nvidias incapability to produce a solid 45nm product on TSMC foundry?
A1) Math shows that 32nm produces nearly double the amount of 45nm chips.
A2) never said transistor count stayed the same. WTF you talking about.
A3) By eyehole I mean something worse and by punch I mean not using any part of my body eww. Defintiley don't want my fist in anyones buttocks.
A4) Per Anything, sorry that is just a ridiculous assumption. Come one. I asked their PR firm about some SSD facts, things knownw on the internet and got called and insider. whatever the **** that means. Dunno, I dont Intel.


A5) to the question you didnt ask. Yes it is cheaper to produce a smaller size than continue to produce the ame thing repeatedly.





You are thinking wrong. Adding transistors has nothing to do with physically adding anything. It is a design etched in acid. Believe it or not, you have no choice on whether it is a cpu or not. Just like you have no choice but to be wrong, because you are. IT isa lithography process and designed before you entered the equation.


First, if you can't have an intelligent debate without resorting to insults and vulgarity than you really shouldn't be posting in a forum such as this.

Second, let's see the "math" that you claim shows "nearly double" the CPU count per wafer.

Third and finally, every time they shift to a new process node, yield per wafer goes down until the process matures. Even more so when using a process with inherent problems that weren't faced with previous nodes such as current leakage due to the ever "thinning" of the walls between traces and gates. Read this again before posting a response and consider what sentences like "IP integration, power, electrostatic discharge, electromagnetic interference (EMI), proximity effects at extreme densities, software development and integration, complex verification and packaging issues", "These cumulative issues are like a perfect storm on the manufacturing side, as well. Just because a chip GDSII database can be delivered to a foundry doesn’t mean the chip can be manufactured with acceptable yield—or that it will actually work and turn into a high-volume production run. It also doesn’t mean that it will work with the existing processes developed by a foundry, which can further drive up the cost of developing a chip. Compounding the problems, at 22/20nm some level of double patterning will be required, and over the next 24 months companies will begin stacking die in 2.5D and 3D configurations using interposers and through-silicon vias (TSVs), respectively."

http://chipdesignmag.com/sld/blog/2011/04/28/manufacturing-challenges-at-22nm-and-in-stacked-die/
 
Dont make me the eyehole. Even if I am one.
2ndly. you saw the math why ask for it again.
3rdly. yield per goes down but not enough to make it untenable.

You really dont get it?

OK hows this, ford comes out with a car... decent engine and it 40 mpg


built and made


they r not going to sell it because Chevy only makes a 25 mpg version?


EDIT: Nm ignore me Im talking about intel on intel and not the chain of discussion for this topic.

EDIT EDIT: OMG I just realized I am on my last 2 beers out of an entire case. I will reread this thread tomorrow and go WTF? First of all how did I drink that much, 2ndly, why do people think a die shrink costs more money and 3rdly I am AWESOME!

Being awesome makes everything easier. Still does not excuse the 2nd part. That is not on me that is on you guys. Really, die shrink is more expensive?
 
Last edited:
Dont make me the eyehole. Even if I am one.
2ndly. you saw the math why ask for it again.
3rdly. yield per goes down but not enough to make it untenable.

You really dont get it?

OK hows this, ford comes out with a car... decent engine and it 40 mpg


built and made


they r not going to sell it because Chevy only makes a 25 mpg version?


EDIT: Nm ignore me Im talking about intel on intel and not the chain of discussion for this topic.

Nothing in this discussion is about "Intel vs AMD". It's about the industry in general. And I haven't seen you're math that supports your assertion of "nearly double" the chips per wafer. What I do know is that the "math" used to give an approximation is this -

Analytical die count estimation

For any given wafer diameter [d, mm] and target IC size [S, mm2], there is an exact number of integral die pieces that can be sliced out of the wafer. The gross Die Per Wafer [DPW] can be estimated by the following expression:



Note, that the gross die count does not take into account the die defect loss, various alignment markings and test sites on the wafer.

As for costs decreasing with advanced node size reduction that you've asserted, I'll say this. 2 things make up the "cost per CPU", cost per wafer and yield per wafer. In order for the cost per "chip" to decrease going from say 32nm to 22nm BOTH must remain relatively the same or close. Let's use a hypothetical CPU "A". On a 300mm wafer we'll say that the entire wafer costs $6000. With a "die" size of 143mm^2 (I'm going to use the 65nm "conroe" size as an example), that comes to 426 dies per wafer. At a 70% yield rate that comes to 298 viable "chips" at a cost of $20.13 each. Now take CPU "B" at a lower node with a "die" size of 107mm^2 (wolfdale @45nm). That comes to 580 dies per wafer (408 viable "chips" at 70% yield). At the same yield rate the cost per wafer cannot exceed $8172.78 for the new "chips" to be equal to or less than CPU "A"s cost per chip. If yield were to decrease to say 50% which means 290 "viable" chips, the cost per wafer cannot exceed $5837.70 in order to be equal to or less than CPU "A"s cost per chip. Now remember that complexity and and thus costs per wafer rise significantly going from 32nm to 22nm. Unless yield rate greatly increases (unlikely) from the last "node size" there is no way that "costs per chip" have gone down.
 
Last edited:
Come on guys, an interesting read but time to chill out a little before things go out of control.

Neruomancer, I get your humor there though not everyone "gets" satirical humor, when making a point with it use some smileys or people get upset. Particularly when the discussion has become borderline argument, people misunderstand it. I know, I've been there before :thup:
 
Come on guys, an interesting read but time to chill out a little before things go out of control.

Neruomancer, I get your humor there though not everyone "gets" satirical humor, when making a point with it use some smileys or people get upset. Particularly when the discussion has become borderline argument, people misunderstand it. I know, I've been there before :thup:

I do that alot I know better than to get online after imbibing but I enjoyed the conversation it was hot here and the beers were so cold. Got carried away. My apologies to anyone I offended. I am going to take a break from discussions for a while, until I can learn to stay on track and not be silly or offensive. I stopped talking to people on IM because, we get really foul and abusive (all in fun of course) but that is one on one chat not forum posting and I stopped doing that so I wouldn't act that way on the forums. apparently not long enough, need a longer stay from forum posting. Sticking to reading not writing for awhile..

As for the math showing number of chips doubled from 45nm to 32nm, I found that info at anandtech. (I assumed his math was correct ;) )

The count was in relation to ARM chips, but I assumed the math was the same.

The original 45nm A5's die measured approximately 122mm^2. The new 32nm A5 has a surface area of only 69mm^2. That's actually amazingly good scaling at 57% of the old die size, as perfect scaling from 45nm to 32nm would be around 50.5%.



Assuming Apple could make full use of a 300mm wafer (which it can't, wafers are round, chips are rectangular at best so there are some unusable chips), Samsung could deliver 579 45nm A5 die to Apple. The move to 32nm would give Apple 75% more die per wafer at 1015 chips. Again both of these numbers are over estimates as they assume full usage of the surface area of a wafer as well as 100% yields, but you can see the benefit of a smaller die. As long as wafer costs increase by a factor less than the 75% increase in number of die per wafer, Apple can effectively reduce SoC cost by going this route.


Here is on on intel chips, does not show number of wafers but does show core sizes
http://www.anandtech.com/show/5875/dual-coregt2-ivy-bridge-die-measured-121mm2

Almost 300 square for p55, 160 square for IB with HD3000 GFX. (pretty impressive) Bulldozer is about hte same if you count per core, using 320square at 8C count.
 
Last edited:
I do that alot I know better than to get online after imbibing but I enjoyed the conversation it was hot here and the beers were so cold. Got carried away. My apologies to anyone I offended. I am going to take a break from discussions for a while, until I can learn to stay on track and not be silly or offensive. I stopped talking to people on IM because, we get really foul and abusive (all in fun of course) but that is one on one chat not forum posting and I stopped doing that so I wouldn't act that way on the forums. apparently not long enough, need a longer stay from forum posting. Sticking to reading not writing for awhile..

As for the math showing number of chips doubled from 45nm to 32nm, I found that info at anandtech. (I assumed his math was correct ;) )

The count was in relation to ARM chips, but I assumed the math was the same.




Here is on on intel chips, does not show number of wafers but does show core sizes
http://www.anandtech.com/show/5875/dual-coregt2-ivy-bridge-die-measured-121mm2

Almost 300 square for p55, 160 square for IB with HD3000 GFX. (pretty impressive) Bulldozer is about hte same if you count per core, using 320square at 8C count.

That's mostly mobile CPU's but the percentage decrease in size is probably roughly the same for the desktop.

Intel Sandy Bridge 2C/GT2 = 149mm^2
Intel Ivy Bridge 2C/GT2 = 121mm^2
Roughly 20% decrease in size which falls in line with what we've seen going from 45nm to 32nm.
 
That's mostly mobile CPU's

Think you hit on something there Bubba. This may have been mentioned earlier and I'm sorry if its already been discussed (full disclosure: skimmed most of the thread), but seems like most of the discussion here is taken from the "desktop perspective".

Were this Vegas, I'd put my Benjamins on low voltage mobile CPUs being the main reason for continued heavy interest in die shrinks in the face of decreasing yields.

We geeks are a tiny component of the computer userbase, and whether we geeks like it or not the desktop as we know it is going away for the general user. As opposed to even five years ago, the job of email checker/youtube viewer/office file manipulator that comprises 99% of what a standard user does can now be handled by a 17W mobile Ivy Bridge or the like with nearly the same aplomb that a desktop C2D handled the task then. I don't think it's any secret to either Intel or AMD that what we'd call a "mobile processor" now is the mainstream market CPU of the future and the mainstream machine will be a mobile device. "Personal Desktop CPUs", such as today's 2600k, will be the exception rather than the rule. They'll be the niche CPU.

Following that logic, low voltage CPU implementations do take particularly well to die shrinks due to the fact that with a linear drop in power, the power density problem becomes more than linearly easier to handle.
 
Back