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Anatomy of a microprocessor?

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Jun 23, 2002
Recently, I asked a few people about how a modern day microprocessor is fabricated. Can anyone shoot me any links on the subject?

One individual offered the following:

"the wafer is surrounded by a heatsink. which is the thing you hold and often call a processor. Its actually the "casing" known as Tc in processor ling. Then you get the heatsink that draws heat away from the casing. thats where you get the "surface" tempreature term from and the "core" tempreature is the tempreature the wafer operates at (usually 200 degrees C -- yes sound slike a lot..but...it burns at about 250c)"

I think this is pretty much BS, but I'd like some input from you guys.


Oct 9, 2003
I think at 200c it would melt :p
And with some mobo's you can read the core temps... that's the temp of the actual core the actual thing that is doing the processing and it's not that hot. As far as the whole caseing thing you will have to wait for someone else's reply....


Jul 14, 2002
The West
Most chips can easily tolerate temperatures of 200-250 C. In fact some parts of the manufacturing process involve temperatures far greater than that.

Semiconductor fabrication is a rediculously complicated process. A detailed overview could easily consume a few textbook volumes. A google search on "semiconductor manufacturing" or "semiconductor process" will give you pleny of info.

Here's one site that has a decent overview with lots of pictures: http://sharif.edu/~hessabi/Adv_VLSI/slides/SEMICOND.HTM


Mar 18, 2002
The Parabolic Quantum Well
NookieN is right in saying semiconductor fabrication is complicated. It is a complex chemical process involving many steps, but here are the basic steps in fabricating today's modern microprocessors: (I am assuming that you know the basic structure of the CMOS transistor)

Modern integrated circuit (IC) fabrication can be broken up into two major parts. Front-end processing, in which the transistors are fabricated, and back-end processing in which the interconnects are fabricated.

1. Isolation structures are created to isolate devices from each other as well as give a rough definition of the active areas (areas were transistors will be located). In today’s modern ICs this is done by a technique called shallow trench isolation (STI). Here a shallow trench is etched into the silicon substrate and filled with high density silicon dioxide.

2. The wells are then isolated and ions of dopant atoms are placed into the wafer to change the electrical properties of the desired regions. These wells will define what will become NMOS and PMOS transistors depending on the type of dopant ions that are implanted and where they are implanted. Other implants are done in this step are done as well such as the punch-through implant to prevent some undesired effects from adding dopant atoms into the wafer and threshold adjust implant to ensure that the turn on voltage of the NMOS and PMOS are symmetrical.

3. Next the gate dielectric is grown or deposited onto the wafer. Currently silicon oxynitride is used as the gate dielectric and is thermally grown on the wafer. As devices become smaller high-k dielectrics are needed in order to prevent a phenomenon known as tunneling. Since high-k dielectrics are a form of native oxide of silicon these are deposited onto the wafer using a technique known as atomic layer deposition.

4. The gate electrode is then deposited onto the wafer on-top of the gate dielectric and patterned. Currently heavily doped poly-crystalline silicon is used as a gate electrode. The gate electrode is often deposited un-doped. The gate electrode is then patterned using optical lithography and dry etch process in which plasma is used to etch the material. (Usually sulfur based chemistry for polysilicon) However as devices become smaller there is a move to metal gate electrode as they do not exhibit some effects such as depletion at the electrode/dielectric interface. Candidate gate material include molybdenum, but using metal gate electrode present their own problems that the semiconductor industry is currently working to solve

5. Next the source/drain extensions are implanted into the wafer. As with the wells, punch-through, and threshold adjust implant, these are done separately for the NMOS and PMOS transistors. Some process also involve what is known as a pocket halo implant, which is another method to prevent punch-through of the source/drain depletion regions. (Punch-through = bad) During this step the polysilicon gate electrodes are also doped. The implants involved in this step, particularly the source/drain extension implants are very shallow, in the order of a couple of nanometers, in order to prevent unwanted effects from scaling the devices (short channel effects).

6. Next a spacer is deposited and etched around the gate electrodes. This is used to protect the source/drain extensions from receiving further dopant atoms from the next implant step.

7. After spacers are created around the gate electrode a deeper source/drain contact implant is done. This is done in order to reduce series resistance from the source/drain extensions to the contact areas of the transistors. Continued doping the polysilicon electrodes are also done in this step as these electrodes require a huge dose of dopant atoms.

8. The dielectric film grown or deposited that are over the source/drain contacts are then etched away and a metal, in today’s modern processes nickel or cobalt, and is then heated at a certain temperature where it undergoes a chemical reaction with the local silicon to create a silicide over the source/drain contacts and the polysilicon gate electrodes. This is done to reduce resistance in the gate electrodes and the contact areas. This step is the end of front-end processing

9. The beginning of the back-end processing begins with a thick layer of inter-level dielectric, usually oxide, is then deposited via chemical vapor deposition, onto the wafers. This dielectric is then patterned with contact cuts and tungsten deposited creating a connection from the transistors to the interconnects that will eventually be fabricated.

10. Another layer of inter-level dielectric (ILD) is the deposited and patterned. Copper is then electroplated to form the first level of interconnects. This is usually done in a process known as the Damascene process.

11. Another ILD is then deposited on top of the first interconnect level. In modern processes this ILD is usually carbon doped oxide, or some type of low-k dielectric. The contacts to the first level interconnects are then patterned followed by the second level interconnects. Copper is then electroplated into the patterned oxide to form the vias and second level interconnect lines. This is known as the Dual Damascene process. This is repeated until all the desired levels of interconnects are fabricated.

12. Once all interconnects are fabricated a passivation layer is then deposited onto the wafer protecting the circuitry beneath and lead contacts are placed as input/output leads for the microprocessor. The microprocessor is then tested and packaged and sent out to the consumer.

These are the basic steps involved in fabricating a modern microprocessor. Of course it gets more involved. If you are interested you can do a Google search or if your library has “Silicon Process for the VLSI Era Vol. 2” by S. Wolf, you can find more in depth information on semiconductor fabrication.