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Here's some quantifiable info...Its been more of a personal experience.
I guess you'll get that second... in some titles. But for me, paying 2x for a second drive isn't worth that second... especially in games that I sit in a lobby and wait for it to populate (Battle Royale guy, lol).But gains are gains, and if I can load into HLL 1 second sooner
Not on my 58X3D lol..At least Cinebench scores look nice
There is barely any difference in the access time and low queue random read between RAID 0 and RAID 1. RAID 0, in a typical scenario, has a higher sequential bandwidth, which doesn't really matter in most tasks (meaning any single SSD has it high enough).Oh man, ADD moment. I swapped RAID 1 and 0 in my brain. Its RAID 0 that I'm using![]()
Yeah I'll keep an eye on it.
I'd really like an ASUS so I can take advantage of their crazy high options of customizing the power ICs. There seems to be a lot of cool options these days with ASUS boards. A lot more since the 300 chipset days when I used them last. And the only reason I would want this feature is to push the X3D CPU to its limit at all times. But We'll see once all this hardware is in the hands of reviewers and testers.
... but I guess what's the point if it's in clock driver bypass anyway...Supports CUDIMM, Clock Driver bypass mode only*
* CUDIMM support and POR boot frequency may vary by CPU series, with manual overclocking available after boot. Certain CPUs may fail to boot, but future BIOS updates will improve compatibility.
I'm not sure what all boards/board partners are like, but the MSI board I looked at first (X870E Carbon) 'supports' CUDIMMs...
... but I guess what's the point if it's in clock driver bypass anyway...
That's the vibe I got with MSI's statement. If it bypasses the clock gen, then is it really a CUDIMM, lol?I'm not sure how it will work, as my current knowledge is based on comments from some manufacturers (and more marketing than someone technical). One of the vendors suggested it would work, but because of support issues, it will work the same as modules without the clock controller, so around 8000-8200MT/s with 7000/9000 series CPUs and up to 8600MT/s with 8000 APUs.
That's the vibe I got with MSI's statement. If it bypasses the clock gen, then is it really a CUDIMM, lol?
Fortunately I am not in a hurry to build but if CUDIMMs can enable affordable 8000+ I'll wait for it. If not running an APU I guess it is less important on AMD side since it'll be choked by internal CPU connectivity anyway, but it could be more interesting on Intel. I can't ignore the potential impact of >30% increase in bandwidth as finally that is something actually faster than my better DDR4 systems. (6000-6400 DDR5 is a side grade at best)I hope it's only at the BIOS level and will be added to AMD, too. On the other hand, I don't expect it to improve general performance by more than 1% (as we already see between 6000MT/s and 8000MT/s).
I think I first noticed this in Zen 3. Due to the limited bandwidth of IF between CCD and IOD, it wasn't possible for a single CCD CPU to max out writes, although reads could get close. You'd have to use a two CCD part to get that up. Zen 4 seemed to do something weird which I never got to the bottom of. It is reported as performing higher than expected given Zen 3, and AMD said they didn't change IF bandwidth. Maybe it is something to do with different async clocks but I never looked into it. I probably should since I finally got Zen 4 earlier this year, but it is not a priority.it feels like there is some kind of bandwidth wall.
I think I first noticed this in Zen 3. Due to the limited bandwidth of IF between CCD and IOD, it wasn't possible for a single CCD CPU to max out writes, although reads could get close. You'd have to use a two CCD part to get that up. Zen 4 seemed to do something weird which I never got to the bottom of. It is reported as performing higher than expected given Zen 3, and AMD said they didn't change IF bandwidth. Maybe it is something to do with different async clocks but I never looked into it. I probably should since I finally got Zen 4 earlier this year, but it is not a priority.
I don't know if APUs work much differently there but I'm assuming logically it works the same way even if it is on same silicon now.
As for CUDIMMs, I'm hoping they'll enable it to be easy to hit higher speeds without only looking at the extreme highest. For example, if it is easier to make a 8000 CUDIMM than a regular 8000 DIMM, maybe it could be cheaper even with the extra chip required. Think I saw somewhere that CUDIMM will be JEDEC standard requirement from 6400 upwards so it will have to be cheap to do in volume.
The Taichi doesn't share lanes with the first PCIe slot, but it only supports one PCIe 5.0 SSD. The Nova has info: "If M2_5 is occupied, PCIE3 will be disabled", but everything else is the same as in the Taichi.Going back to the first post, what boards share lanes between M.2 and actual slots? I've not seen one, regardless of chipset ever do that. Looking at Asrock, The Taichi doesn't. Can't find deets on ASUS boards yet.
You'll see this on X870 more than X870E as there are fewer lanes available. ASRock PG Riptide loses the second PCIe slot for M.2, for exmaple. But it happens on X870E, too.Going back to the first post, what boards share lanes between M.2 and actual slots? I've not seen one, regardless of chipset ever do that. Looking at Asrock, The Taichi doesn't. Can't find deets on ASUS boards yet.