HUN_Invisible
New Member
- Joined
- Jan 16, 2019
- Location
- Hungary
Good guide batboy.
I am just wondering if the following process I am going to describe is good or not as a first step for memory overclocking:
Lets assume we have a memory module with 14-14-14-34 timings @ 3200MHz.
As far as I know the latencies are provided in terms of clock cycles. Which means in case of 14 the latency is 1/3200MHz*14Cycles = 8.75ns which is a pretty good timing. If we want to use the memory module @ 4000MHz than the latencies shall be set (as a starting point) to 1/3200MHz*14Cycles*4000MHz = 17.5 ~ 18 and 1/3200MHz*34Cycle*4000MHz = 42.5 ~ 43. So @4000MHz first I would set the timings to 18-18-18-43. This setting shall be stable, and - of course - the voltages shall be raised, as well as you have mentioned. Then I would do a performance test to check if it is really stable or not. And as a next step I would lower the values by 1 and do the performance test again. I would do this until I find the minimum timings in case of each values.
In case of your memories the process gives -lets say - right result.
You have 15-15-15-35@3600MHz which (with the given formula) is 18-18-18-40@4200MHz. And thanks to your effort we know that those modules work with 17-17-17-36@4200MHz. It means that by lowering timing value by 1 we can get the thoughest timing in 7 steps which is not too much, I guess.
What do you think, would this process work?
I am just wondering if the following process I am going to describe is good or not as a first step for memory overclocking:
Lets assume we have a memory module with 14-14-14-34 timings @ 3200MHz.
As far as I know the latencies are provided in terms of clock cycles. Which means in case of 14 the latency is 1/3200MHz*14Cycles = 8.75ns which is a pretty good timing. If we want to use the memory module @ 4000MHz than the latencies shall be set (as a starting point) to 1/3200MHz*14Cycles*4000MHz = 17.5 ~ 18 and 1/3200MHz*34Cycle*4000MHz = 42.5 ~ 43. So @4000MHz first I would set the timings to 18-18-18-43. This setting shall be stable, and - of course - the voltages shall be raised, as well as you have mentioned. Then I would do a performance test to check if it is really stable or not. And as a next step I would lower the values by 1 and do the performance test again. I would do this until I find the minimum timings in case of each values.
In case of your memories the process gives -lets say - right result.
You have 15-15-15-35@3600MHz which (with the given formula) is 18-18-18-40@4200MHz. And thanks to your effort we know that those modules work with 17-17-17-36@4200MHz. It means that by lowering timing value by 1 we can get the thoughest timing in 7 steps which is not too much, I guess.
What do you think, would this process work?