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Fermi officialy delayed..

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Shiggity

Member
Joined
Dec 16, 2007
Location
Chicago, IL
I thought this was already common knowledge.

Fermi in 2009 was never ever going to happen.

TMSC's 40nm process is so shady atm, it could easily be delayed longer. AMD will have non-stop headaches trying to keep 5xxx supply up for the holidays as well. 3rd party price gouging inc ;)
 

Tyranos

Member
Joined
Jul 20, 2001
Location
NM
I thought this was already common knowledge.

Fermi in 2009 was never ever going to happen.

TMSC's 40nm process is so shady atm, it could easily be delayed longer. AMD will have non-stop headaches trying to keep 5xxx supply up for the holidays as well. 3rd party price gouging inc ;)

Shady how?
 

Shiggity

Member
Joined
Dec 16, 2007
Location
Chicago, IL
We’ve talked previously about TSMC – the foundry both NVIDIA and AMD GPUs are manufactured at – having yield issues with their 40nm process. This first surfaced with the Radeon 4770, which at the time of its introduction was being built while TSMC’s yields were below 40%, and this coupled with its popularity made for a significant shortage around its introduction. TSMC continued to improve their yields, and by the time of the Radeon 5000 series launch, AMD told us that they weren’t concerned with yields. As of this summer, TSMC was reporting yields of 60%.

On Friday the 30th, Digitimes broke the word that TSMC’s yields were back down to 40%. This we believe is due to issues TSMC is having ramping up overall 40nm production, but regardless of the reason it represents a 33% drop in usable chips per 40nm wafer. When you’re AMD and you’re rolling out a top-to-bottom 40nm product line in a 6 month period, this is a problem.
http://www.anandtech.com/weblog/showpost.aspx?i=654
 

Tyranos

Member
Joined
Jul 20, 2001
Location
NM
Thanks. I'll have to see if I can get a 45n manual to confirm my suspicion. I was assuming that "40n" was simply Nvidia's usual marketing ploy. In every TSMC DRM, you have the option to shrink or enlarge the process by a certain percentage and in certain areas according to very specific design rules such as vertical interconnect spacings, etc. Historically, Nvidia used that to shrink the process a tiny bit and market it as a "new technology" on their video cards. Other companies do this too of course.

But, it's probable that TSMC only shrunk the process by 5nm this time around as their official release instead of going to 35n.
 
OP
ratbuddy

ratbuddy

Member
Joined
Aug 24, 2007
Thanks. I'll have to see if I can get a 45n manual to confirm my suspicion. I was assuming that "40n" was simply Nvidia's usual marketing ploy. In every TSMC DRM, you have the option to shrink or enlarge the process by a certain percentage and in certain areas according to very specific design rules such as vertical interconnect spacings, etc. Historically, Nvidia used that to shrink the process a tiny bit and market it as a "new technology" on their video cards. Other companies do this too of course.

But, it's probable that TSMC only shrunk the process by 5nm this time around as their official release instead of going to 35n.

The last round of video cards were done on 55nm, not counting the (crummy yield) HD 4770. The new ones (HD 5 series and Nvidia's new stuff) are going down to 40nm.
 

Tyranos

Member
Joined
Jul 20, 2001
Location
NM
Yes, the 55n cards were simply using the shrink option available for customers that had the 65nm DRM's and PDK's. I'd have to see a 45n manual to determine whether or not the "40n" process is also that. The eetimes reports the same **** poor yield, so either 40n is a brand new process or TSMC had unforseen consequences that cropped up when letting the customers tape out on a 90% 45n option.
 
OP
ratbuddy

ratbuddy

Member
Joined
Aug 24, 2007
Yes, the 55n cards were simply using the shrink option available for customers that had the 65nm DRM's and PDK's. I'd have to see a 45n manual to determine whether or not the "40n" process is also that. The eetimes reports the same **** poor yield, so either 40n is a brand new process or TSMC had unforseen consequences that cropped up when letting the customers tape out on a 90% 45n option.

I sorta doubt it, their 45nm process was introduced quite a while before 40nm. Check out http://www.tsmc.com/english/b_technology/b01_platform/b010101_45nm.htm and http://www.tsmc.com/english/b_technology/b01_platform/b010101_40nm.htm
 

Tyranos

Member
Joined
Jul 20, 2001
Location
NM
I see the 45n link, but it doesn't show up in their official list. I can't say anything for certain until I see some manuals. Processes are confidential so the info isn't going to be floating around on the net, which is why most of us that work/worked in this industry take "tech" reports from enthusiast sites like anandtech, toms, etc with a grain of salt.

If you look at the TSMC website, you see 130, 90, 65, 55, and 40. I haven't worked with 40, but for the 300, 190, 130, 90, and 65, there was always the process shrink option IIRC. It's rather silly of them to actually list "55n" because a 55n dedicated DRM doesn't exist. The rules dictating "55n" are simply optional shrink rules that customers originally received in the 65n DRM (or one of the later revisions of those manuals). They don't list "80" nm, yet Nvidia harped on that even though it was an optional die shrink from 90nm.

I stopped working as a process engineer before I had a 4x TSMC manual in my hands, but I find it strange that a 45n process from TSMC supposedly exists, yet they list 40n as the official process. Seems like they are taking advantage of marketing and using the 45n process they originally developed but with the die shrink option. They might be trying to look like they are leapfrogging the IBM/AMD/Freescale 45nm process (which I also have extensive experience with). But again, until one of my colleagues can hook me up with the new manuals, it's neither here or there.
 
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