- Joined
- Nov 25, 2001
- Location
- Niagara Falls, Ontario, Canada
Hi guys,
Okay, I know which bridges control the cache, per ...
http://www.beachlink.com/~candjac/PaloDecode0.htm#L2/L9
and
http://fab51.com/cpu/palomino/athlon-e5.html
and
http://fab51.com/cpu/barton/athlon-e23.html#L2
But I'm wondering if there is any way to detect which banks of cache may be bad and relate that to a bridge configuration that selectively disables the bad area?
I mean it looks like there were some durons around with more than one L2 cut, most of the ones that were successfully cache unlocked appeared only to have single (default downbinned?) cuts, but I'm guessing the ones that actually had a cache fault configured out, most often had a couple of cuts.
So you might be wondering what the hell I'm trying to do. Well I've got a tbred here that I bought knowing it had "issues" and all the signs seem to point to the L2 cache being faulty. The mobo I have it on right now doesn't seem to support disabling L2 cache in BIOS though, I'm going to check my other mobos for this feature though. I'm figuring memtest might help with the identification of the addresses of the bad area, but some info on relating that to the bridge settings would be good. Other suggestions of DOS or selfbootable diags to test it with would be welcome though.
What I would like to achieve is to disable the minimal amount of cache possible, hopefully only 128k of the 256. This will of course give me the wierdest tbred ever, but what the hell, it will probably still do some useful folding. But even if I have to settle for all but 64K disabled I'll still have a "duron".
I don't think this is a remark from an applebred, the bridges look real clean, and the label looks right. It's absolutely no use to me to know whether it is a remark or not, I still need to know how to config the cache.
Of course I could do this by trial and error, but considering the difficulty of modding the bridges on the later style chips and how delicate they are, I think my bridges may get FUBAR'ed before I get to where I want to be. Also it will probably take a week solid of screwing with it.
Ideally I'd like to hear from people with applebreds that wouldn't take a full 256K mod, and who managed maybe to get 128K and how they identified which 128K to to use.
I may end up building that switch block on Fab51, but I dunno how successful connecting the L9s might be.
thanks in advance for any insight,
Road Warrior
Okay, I know which bridges control the cache, per ...
http://www.beachlink.com/~candjac/PaloDecode0.htm#L2/L9
and
http://fab51.com/cpu/palomino/athlon-e5.html
and
http://fab51.com/cpu/barton/athlon-e23.html#L2
But I'm wondering if there is any way to detect which banks of cache may be bad and relate that to a bridge configuration that selectively disables the bad area?
I mean it looks like there were some durons around with more than one L2 cut, most of the ones that were successfully cache unlocked appeared only to have single (default downbinned?) cuts, but I'm guessing the ones that actually had a cache fault configured out, most often had a couple of cuts.
So you might be wondering what the hell I'm trying to do. Well I've got a tbred here that I bought knowing it had "issues" and all the signs seem to point to the L2 cache being faulty. The mobo I have it on right now doesn't seem to support disabling L2 cache in BIOS though, I'm going to check my other mobos for this feature though. I'm figuring memtest might help with the identification of the addresses of the bad area, but some info on relating that to the bridge settings would be good. Other suggestions of DOS or selfbootable diags to test it with would be welcome though.
What I would like to achieve is to disable the minimal amount of cache possible, hopefully only 128k of the 256. This will of course give me the wierdest tbred ever, but what the hell, it will probably still do some useful folding. But even if I have to settle for all but 64K disabled I'll still have a "duron".
I don't think this is a remark from an applebred, the bridges look real clean, and the label looks right. It's absolutely no use to me to know whether it is a remark or not, I still need to know how to config the cache.
Of course I could do this by trial and error, but considering the difficulty of modding the bridges on the later style chips and how delicate they are, I think my bridges may get FUBAR'ed before I get to where I want to be. Also it will probably take a week solid of screwing with it.
Ideally I'd like to hear from people with applebreds that wouldn't take a full 256K mod, and who managed maybe to get 128K and how they identified which 128K to to use.
I may end up building that switch block on Fab51, but I dunno how successful connecting the L9s might be.
thanks in advance for any insight,
Road Warrior