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Help! How to selectively disable tbred cache banks????

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RoadWarrior

Senior Member
Joined
Nov 25, 2001
Location
Niagara Falls, Ontario, Canada
Hi guys,

Okay, I know which bridges control the cache, per ...

http://www.beachlink.com/~candjac/PaloDecode0.htm#L2/L9
and
http://fab51.com/cpu/palomino/athlon-e5.html
and
http://fab51.com/cpu/barton/athlon-e23.html#L2

But I'm wondering if there is any way to detect which banks of cache may be bad and relate that to a bridge configuration that selectively disables the bad area?

I mean it looks like there were some durons around with more than one L2 cut, most of the ones that were successfully cache unlocked appeared only to have single (default downbinned?) cuts, but I'm guessing the ones that actually had a cache fault configured out, most often had a couple of cuts.

So you might be wondering what the hell I'm trying to do. Well I've got a tbred here that I bought knowing it had "issues" and all the signs seem to point to the L2 cache being faulty. The mobo I have it on right now doesn't seem to support disabling L2 cache in BIOS though, I'm going to check my other mobos for this feature though. I'm figuring memtest might help with the identification of the addresses of the bad area, but some info on relating that to the bridge settings would be good. Other suggestions of DOS or selfbootable diags to test it with would be welcome though.

What I would like to achieve is to disable the minimal amount of cache possible, hopefully only 128k of the 256. This will of course give me the wierdest tbred ever, but what the hell, it will probably still do some useful folding. But even if I have to settle for all but 64K disabled I'll still have a "duron".

I don't think this is a remark from an applebred, the bridges look real clean, and the label looks right. It's absolutely no use to me to know whether it is a remark or not, I still need to know how to config the cache.

Of course I could do this by trial and error, but considering the difficulty of modding the bridges on the later style chips and how delicate they are, I think my bridges may get FUBAR'ed before I get to where I want to be. Also it will probably take a week solid of screwing with it.

Ideally I'd like to hear from people with applebreds that wouldn't take a full 256K mod, and who managed maybe to get 128K and how they identified which 128K to to use.

I may end up building that switch block on Fab51, but I dunno how successful connecting the L9s might be.

thanks in advance for any insight,

Road Warrior
 
okay this was hard to find I'll post my L2 setup on a duron750

hmm this doesn't have the same bridges.....

. | | L2
 
In the bios you can disable all cache then you will be left with like 32k level 1 cache. Gonna suck for gaming but hopefully still be alright for folding
 
Thanks for the trouble el but yeah, that one would be a spitfire core which isn't the same as the duron applebreds and XP thoroughbreds.

Well in the KG7's BIOS I don't have the option to disable L2 unfortunately. Maybe I'll try and see if it's there to unlock with AMIBCP or something though because that would possibly be easier than tearing another rig down to use the mobo. My K7S5A has it. Dunno about folding with no L2 cache whatsoever though, would prolly be like folding with a PII (since DDR is probably as fast as the L2 on those) Though the tbreds have 64Kb+64Kb L1 data and instruction cache.

Road Warrior
 
Might just be easier to ebay the cpu to someone who has a mobo that can disable the cache and get a fully working one, there like $30 for an xp1700. 1.46GHz stock, tbred A expect 2GHz, tbred B expect 2.3GHz average
 
I realise this, that's why I wanna find the bad part of the 256K and config it out for 128k or 64K as is done on the durons, which are only a couple of percent slower than full tbreds on most stuff clock for clock.
 
Never heard of software that can disable cache or test only part of enabled cache.

This may end up as being a mod-remod approach only but I'm looking forward to finding out if you end up finding a way to do a test without physically disabling part of the cache.


As for those of us that tried the cache enabling mods, -- (spent a lot of time trying to enable cache on one of the first superlocked CPUs ever made in 2003 before we knew what 'superlocked' was :bang head) --, I believe there were some discussions over the years pointing to there not being many Applebreds or Thortons with bad cache out there. It was said that all those CPUs have good cache that has simply been disabled for marketing purposes but then somehow it became accepted opinion that Thortons were made out of Bartons with bad cache, etc, which wasn't the case, few had bad cache...

Good luck.
 
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