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help understanding AMD and Intel Bus Speeds

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theMonster

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Jul 22, 2004
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At the pub
I'm a bit confused on the Intel and AMD bus speeds. I have an XP mobile 2600 at this point but will go dual-core later this year and want faster memory NOW. In trying to decide what speed to get, I'm getting confused on something.

How can AMD and Apple for that matter say they have a 1GHZ memory bus, then Intel say they have one in the 800s when the fastest DDR I've seen is PC5000 or 250MHZ?

Is it on a multiplier now or something? Like 250mhzx4 or are they counting 250mhz per pipe with 4 pipes in HyperTransport? I doubt the latter is the case because then how would Intel be getting bus speeds in the 800mhz range.

Anybody know?
 
Intel has a 200MHz QDR bus (data is transfered 4 times per clock), they also genrally have daul channel DDR, so 2x 200MHz sticks of ram would fill the bus, bandwidth-wise. AMD CPUs have the memory controller built into the cpu, so the memory interfaces with the cpu directly. All system traffic goes over the 1GHz (200MHz x 5) Serial Hypertransport Bus (ther's a 1GHz uplink and a 1GHz downlink).
 
So Iwas right, basically and if I OC my memory to 250mhz or use DDR5000 then I'll get 250x5 or 1.25ghz bus speed?
 
Yes, but the HyperTransport multi is adjustable, so you could lower it to x4 and have a 1GHz hypertransport speed (remember, this won't affect your memory bandwidth at all).
 
It won't? I'm confused again. The jist of this, then is that if I'm running an Athlon XP at 11x250 or 2.75ghz and then I run an Athlon64 with 250mhz memory then the A64 is no faster than the XP on the memory bus side? How would that compute, would it be 250x4(HTT)x3(mem bus multiplier) for 3ghz?
 
If you run an athlon XP at 250MHz FSB speed and an athlon 64 with a memory speed of 250MHz (I believe the memory usually runs at the Hypertransport speed, or off a divider), thhey will both have the same thoeretical bandwidth. But, the Athlon64 will have much lower latency on memory access. This is because the memory controller is on-die, so the cpu talks straight to the memory instead of talking to the northbridge then to the memory.

Remember, in the K8, the memory is not on the Hypertransport bus, the cpu communicates directly to it. THe only thing that goes over the Hypertransport bus is I/O traffic and the like. For a good look at the architecture of the K8, look here:
http://arstechnica.com/articles/paedia/cpu/amd-hammer-1.ars

edit: another k8 link:
http://anandtech.com/cpuchipsets/showdoc.aspx?i=1815

here is where it talks about the memory controller:
http://anandtech.com/cpuchipsets/showdoc.aspx?i=1815&p=6
 
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