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syberspy9

Member
Joined
Sep 4, 2003
Location
Salmon Arm BC CANADA
im not dumb i just havent been told any thing about the intel P4 setup thats inside the cpu.

i know how fsb, vcore and mhz works
what i wana know is how does L1 L2 L3 cach work???
i have a intel P4 2.8C and i understand that the cach 's are memory built into the cpu that makes it work faster.

but what does it store there? what i last opend??? if so when does the cach get cleared or over written?? because i understand that once the L1 is full it goes to L2 and then L3 but then what??

i didnt see a sticky about this so im here to ask.
 

MisterEd

Member
Joined
May 10, 2004
Location
Alabama
A CPU can read/write to cache memory because the link to it is faster than that to main memory. This also means that the cache memory has to be faster and more expensive than the normal SDR and DDR types. A program first looks in cache to find its data. If it is not there then it loads a block at a time from main memory. If the data is not in main memory then it looks in virtual memory. If the program is sequential in memory access then the next data access should be in cache. If the program jumps around in memory then the block of memory in cache must constantly be dumped and reloaded. The more the program can run from cache (without reloading it) the faster it can run.
The following is the order of program access:
CPU registers (fastest access, smallest size, higest cost)
L1 cache
L2 cache
L3 cache
main memory
virtual memory (swap file on disk)
secondary storage (ex. disk drive) (slowest access, largest size, lowest cost)

The higher you can run in this hirerarchy the faster the program can run. As you can see it is a matter of economics. An example of where this is less a concern is the Intel Xeon CPU. One of the reasons Xeons are more expensive is that they have larger cache sizes than P4s. Users of Xeons need the larger caches for performance of their servers. In other words a larger cache allows more of the program to stay there before it must be dumped and main memory accessed.
 
OP
syberspy9

syberspy9

Member
Joined
Sep 4, 2003
Location
Salmon Arm BC CANADA
""If the program jumps around in memory then the block of memory in cache must constantly be dumped and reloaded. ""

thats what i wanted to hear i think........... i dont get it 100%
 

Syx

Member
Joined
Jul 12, 2004
Location
Lake Bodom
The Cache memory operates at the clock speed of the processor, so it means that 512kb of cache is running at 2.8GHz, which is alot faster than any RAM can compare to.
 

batboy

Senior Moment
Joined
Jan 12, 2001
Location
Kansas, USA
That's not a true Northwood. It's a cross between a Northwood and a Xeon.

CPU cache takes care of itself. You can't physically clear it unless you reboot.
 

Drec

Member
Joined
May 23, 2004
batboy said:
High speed L1 and L2 cache is super expensive. That's partly why the P-4 EE's cost so much.

and thats why celerons are so cheap :p
 

diehrd

Senior SMP Gawd
Joined
Jan 15, 2001
Location
NY
The performance gain is what you are paying for..The idea Cache is expensive is slightly skewed.
 

DanIdentity

Member
Joined
May 30, 2004
syberspy9 said:
i know that they will never do it but why dont they make the chips bigger? not taller but wider ect i mean by like 5mm or sommthing?

You mean physically bigger? Because the idea is to reduce size, not increase it. If you increase a chip's physical size you increase the distance of the interconnects between transistors, which would make the chip slower. The chip would also dissipate more power, run hotter, and would require an even bigger cooling mechanism.
 

Sjaak

Member
Joined
Apr 26, 2004
Location
The Netherlands
bigger chips will also be much more expensive because there will be ALOT of bad ones due to bad silicon. with a smaller die size,more chips fit on a single wafer, so they can be produced cheaper.

use the search for alot of extra info...i remember there was a big topic about this a few months ago
 
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