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Intel Architecture Day 2021 info

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Mar 7, 2008
Loads of info, although not complete info by any means on Alder Lake.

  • DDR5 at 4800 confirmed. 128-bit wide support same as DDR4 consumer platforms, so two modules for best performance. Note each DDR5 module has two 32-bit channels instead of 1 64-bit channel in DDR4.
  • PCIe 5.0 confirmed, with up to 16 lanes from CPU. Also 4 PCIe 4.0 lanes e.g. for storage.
  • Top chipset will support up to 12 lanes of PCIe 4.0 and 16 lanes of 3.0.
  • TDP of top part will be 125W.
  • P-cores 19% IPC improvement over Rocket Lake.
  • E-cores better than Skylake at same thread count (HT on Skylake) - don't think it would beat it core per core.
  • Built on Intel 7 process (formerly known as 10 SFE).
  • AVX-512 support removed from consumer offerings.
  • Probably requires Win11 for best performance.

We got some GPU related news too.

First Arc offering will be made on TSMC N6 process. Similar performance but higher density than N7 process. It was announced before today they are due to launch 2022Q1. Anandtech's estimate at FP32 performance puts it around 3060 Ti level, but FP32 does not necessarily scale with gaming performance. Still, if they can offer a competitive mainstream card it could do well. They can work their way up in future generations like AMD are doing.

XeSS will be their competitor to DLSS/FSR. When run on Arc will use AI, falls back to another mode on other/older GPUs so offers wide support like FSR. Uses temporal and spatial info like DLSS 2.0. Will be open sourced.

I am super excited to see how well this low and high performance core layout works. I am a little surprised it took this long to be integrated since smart phones have been using something similar for many years.

I am thinking about holding out for DDR5 build. Or seeing if new layout makes older zen3 drop in price enough.