Ivy Bridge- Did anyone notice the TT article 3770k vs 3570k temps?

[dominick32]

Pretty soon we will know the retail results fellas. NDA almost lifted!

Dom

 

[diaz]

im thinking this chip will benefit greatly from a good lapping/mirror finish.

 

[wingman99]

Trigate yes, and also smaller die = higher power density = higher core temps. And who knows if further design improvements will help, or what die attach currently using.

Acualy the Density is proportional, it is 22nm smaller circutry means there is the same space in-between the transistors and tracers everything is smaller. It would of run cooler like going from 45nm to 32nm however the tri-Gate has a higher power density.

Intel QUOTE On the right: 3-D Tri-Gate transistors form conducting channels on three sidesof a vertical fin structure, providing “fully depleted” operation
Transistors have now entered the third dimension!

On the left is a standerd transistor.

 

[RGE]

Acualy the Density is proportional, it is 22nm smaller circutry means there is the same space in-between the transistors and tracers everything is smaller.

proportionality of space to transistor isnt relevant to power density. More transistors per unit area is, irrespective of proportionality. All die shrinks since increase transistors per unit area will increase power density. See definition in bold below.

I know you are crusading against trigate, but it isnt going away, since some experts, including intel think currently necessary to continue moores law in an economical fashion...until better technologies arrive.

And honestly not interested in continuing a discussion of trigate, when I can read factual information from credible engineering articles if interested.

Power density

Power Density

The amount of power that a chip dissipates per unit area is called its power density, and there are two types of power density that concern processor architects: dynamic power density and static power density.
Dynamic Power Density

Each transistor on a chip dissipates a small amount of power when it is switched, and transistors that are switched rapidly dissipate more power than transistors that are switched slowly. The total amount of power dissipated per unit area due to switching of a chip’s transistors is called dynamic power density. There are two factors that work together to cause an increase in dynamic power density: clockspeed and transistor density.

http://arstechnica.com/old/content/2007/01/8716.ars

You'll note that the move to 3D Tri-Gate transistors doesn't negatively impact transistor density. In fact Intel is claiming a 2x density improvement from 32nm to 22nm (you can fit roughly twice as many transistors in the same die area at 22nm as you could on Intel's 32nm process).

http://www.anandtech.com/show/4313/...nm-3d-trigate-transistors-shipping-in-2h-2011

 

[wingman99]

proportionality of space to transistor isnt relevant to power density. More transistors per unit area is, irrespective of proportionality. All die shrinks since increase transistors per unit area will increase power density. See definition in bold below.

I know you are crusading against trigate, but it isnt going away, since some experts, including intel think currently necessary to continue moores law in an economical fashion...until better technologies arrive.

And honestly not interested in continuing a discussion of trigate, when I can read factual information from credible engineering articles if interested.

Power density


http://arstechnica.com/old/content/2007/01/8716.ars


http://www.anandtech.com/show/4313/...nm-3d-trigate-transistors-shipping-in-2h-2011

That is exactly what i have been saying there is more power density in the TRI-gate transistor when overclocking.

Im not agentst the tri-gate, it's just the cause of the problems now for overclockers.

The IB runs fine stock.
To me it's like bulldozer allot of tech with little results now.

Here is intels PDF on tri gate it's what gets it hot overclocking.
QUOTE:Inversion layer area increased for higher drive current LINK:http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Announcement_Presentation.pdf

EDIT: I reread and reread to see what you are getting at.

The article you posted on power density said cramming more transistors in same amount of surface area increased power density.

However there is 47.3% more surface area with 22nm compared to SB so there is no cramming involved.