No the frequency should remain unchanged. The latency is the delay in clocks between when data is requested and when it is valid on the output lines. It is similar to CAS latency on ram (except that CAS is only one of several delays before data is valid out of ram).
Hehe it's often the other way around: lowering the latency may mean you'll have to decrease the memory speed for stability's sake.
Cache latency follows the same principles as RAM timing does. It's the time delays take in the involved chips between data operations. And yes- less is better and taxes the chips more. That is also the reason why "CL2" RAM is more expensive than commoner's fare. =)