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latency

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hec

Registered
Joined
Jul 16, 2001
I'm no expert i'm guessing based on experiments and thought

If your application is running every device AND
all devices need equal attention

Take the number of devices and multiply it by your FSB

if the answer is equal to your CPU clock speed then

Set latencies equal and divisible by smallest data chunk

too little clock cycles
amount of latency, try to allow it enough clock cycles so that you don't slow down due to too much switching. Switching might probably require one clock cycle (again guessing).

Too many clock cycles will result in too much data- not as much cached data will make less use of CPU

individual tuning- devices which require less attention, lower latency little by little for individual- too low will slow down devices that require data from this device.

lowering latency on one device is like raising it on all others... raising CPU latency is like lowering latency on all others- in the way the the FSB gives it its attention.


ACME CASE
Anthlon 1G
bcm IN730SE
100mhz double data FSB (200mhz fer some but not all)
voodoo3 3000 166mhz@204mhz
256 ram
 
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