PovGRide742
New Member
- Joined
- Apr 8, 2021
This is going to be a long post. I've already started the overclocking journey and my results (further down) and any questions I have are in bold, but first...
Details and Goals:
First Steps:
Hiccup:
Following Steps:
Confusion / Questions for Next Steps:
Again, very long post, but I try to be as thorough as possible to answer any questions that might come up ahead of time. Thanks ahead of time to anyone who takes the time to read this and/or provides insight!
Details and Goals:
- Platform: 11900K (ABT enabled, MCE disabled, no overclock), ASUS STRIX Z590-E
- Memory: F4-3600C14-32GVK (2x16GB DDR4-3600 14-15-15-35 1.45V)
- Personally Set Limits:
Stay under 1.5V DRAM voltage
Stay in Gear 1I know the minor penalty for going Gear 2 can easily be made up for with higher frequencies, but being that I mainly game and the gaming benchmarks out there so far show performance falling off after ~4000MHz, so I would rather the low CAS latency and stay in Gear 1Retain CL14 - Guide used:
- Stress Tests used:
MemTest86 (Right from UEFI) - To make sure it'll still boot and function in Windows
Karhu Ram Test - To test for stability - Benchmark used:
AIDA64 Extreme
First Steps:
- Find my limit in Gear 1:
XMP II turned on and manual settings of 100:133, 1:1, and 3733 but DRAM voltage left at 1.45V boots but errors almost instantly in MemTest86
XMP II turned on and manual settings of 100:133, 1:1, 3733, and 1.5V DRAM boots and passes at least one pass of MemTest86
XMP II turned on and manual settings of 100:133, 1:1, 3866, and 1.5V DRAM fails to boot (even with VCCIO (Memory) and VCCSA set to Auto which are already pretty high (close to if not higher than 1.5V)
Being that the real world latency of 3866 CL15 is higher than that of 3733 CL14, I don't bother trying at CL15 and settle for 3733 CL14 as my Gear 1 limit - Determine baseline primary timings:
Basically, I went on G.SKILL's website and found the lowest CL14 primary timings (14-14-14-34)
Enabled XMP II, manually set 100:133, 1:1, 3733, 1.5V DRAM, 14 tRCD, 14 tRP, and 34 tRAS
After passing one pass of MemTest86, determined 14-14-14-34 as my baseline primary timings
Hiccup:
- XMP I and II set tWR to 'Auto' and the BIOS doesn't give a readout, so I don't have a baseline tWR
Following Steps:
- Using the guide linked above, I first set the suggested 'tight' timings for tRRDS, tRRDL, tFAW, and tWR as 4, 6, 16, and 12 respectively
Passes one pass of MemTest86
- Set tRRDS, tRRDL, tFAW, and tWR to the suggested 'extreme' timings of 4, 4, 16, and 10 respectively
Passes one pass of MemTest86
- Seeing that the next step is setting tRFC, which appears to be a lot of trial and error, I decide to do a 6400% coverage stress test using RAM Test:
0 errors at 6415% (2:32:36, 26154mb tested)
Confusion / Questions for Next Steps:
- After each change, I run AIDA64 3-5 times (SEE ATTACHED TABLE)
If you don't count my 3rd set of settings (which somehow had a freakishly low latency one run compared to the others), my 4th set of settings have the best average 'Read', 'Write', and 'Latency'.
Changing from the suggested 'tight' timings of tRRDS, tRRDL, tFAW, and tWR to the suggested 'extreme' timings, performance drops off in the 5th set of settings (0 errors at 6415% coverage). Does this seem odd? Can going too low, even if it's stabile, cause a performance loss? Should I revert back to my 4th set of settings before diving into tRFC? - Dependent on the questions directly above, can tRRDS, tRRDL, tFAW, and tWR be set even lower than 4, 4, 16, and 10 respectively? And if so, should I even bother?
- The guide linked in the beginning describes how to tune tRFC
How do you go about tuning tRFC2 and tRFC4?
- Not that I'm at this point in the process per the guide linked above yet, but can tRCD/tRP be set lower than the CAS latency (tCL)? (Assuming no, and probably the stupidest question I'll ask)
- After I'm done with tRFC, tRFC2, tRFC4, the tertiary timings mentioned in the guide linked above, revisiting the primary timings (or just tRAS if tRCD/tRP can't be lower than tCL), and seeing if 1T works (leaving it at 2T if it doesn't), should I start dropping the DRAM voltage until I'm no longer stabile or just leave it at 1.5V? If so, in what increments do you recommend?
- VCCIO (Memory) and VCCSA are on Auto and read high (close to if not above 1.5V). I read that 1.25V to 1.45V should be sufficient up to 4000 or 4400MHz. After my timings are finalized and confirmed stabile, should I manually set these to 1.45V and start dropping until I'm stabile? If so, in what increments and before or after dropping DRAM voltage until stabile?
Again, very long post, but I try to be as thorough as possible to answer any questions that might come up ahead of time. Thanks ahead of time to anyone who takes the time to read this and/or provides insight!