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To answer the first part, in synthetic benchmarks it seems the bandwidth is increased, but so is the latency. In some applications I use (Prime95, LLR) the performance difference going from dual to single rank is significant, with single rank memory resulting in ~20% slower app performance if ram speeds/timings are otherwise the same. I suspect the synthetic benchmarks are not exercising the ram in the way the application does so doesn't show as great a difference.
Not saying it is the same thing going on, but it may be a parallel to hard disks. You might have two with similar sustained transfer rates, but one might be significantly better at IOPS.
https://en.wikipedia.org/wiki/Memory_rankA memory rank is a set of DRAM chips connected to the same chip select, which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate (but the data pins are shared across ranks).
The term “rank” was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64 bit wide data bus (72 bit wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths. For example, a rank of x8 (8 bit wide) DRAMs would consist of eight physical chips (nine if ECC is supported), but a rank of x4 (4 bit wide) DRAMs would consist of 16 physical chips (18 if ECC is supported). Multiple ranks can coexist on a single DIMM, and modern DIMMs can consist of one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).
There is little difference between a dual rank UDIMM and two single rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs. The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM is mainly intended to increase the memory density per channel. Too many ranks in the channel can cause excessive loading and decrease the speed of the channel. DRAM load on the CA (Command/Address) bus can be reduced by using registered memory.