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"New DDR4-4333 memory works only on ASRock Z170M OC Formula"

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Shiozaki

Member
Joined
Apr 13, 2014
Are these still not available? i cant find them... they were to come in yellow to match the board, was hoping to buy the kit.

meh.
 

Woomack

Benching Team Leader
Joined
Jan 2, 2005
There are many kits not available in mass sales. It's hard to pick many IC that will run at DDR4-4333 settings. There are other Trident Z which are black/yellow and cost less. On most motherboards you won't be able to set more than ~4133 anyway ( on some not even 3600+ ) and anything past 3733 is way too overpriced.
Personally I recommend Trident Z 3200 CL14/15 or 3600 CL16. Both should run at 4000/1.35V and relaxed timings.

I don't know what motherboard you have but from ASRock only OC Formula runs above 4000 without issues. ASUS has maybe 2-3 boards from ROG series but even Hero/Extreme can't make much more than 4000. From MSI you can find couple models that have guaranteed 4266. I don't know what about Gigabyte but most users have problems with them above 3200-3600.
4333 kit is simply designed for OCFM which has shorter traces than regular boards and is more like ITX board on micro ATX PCB.
 
OP
S

Shiozaki

Member
Joined
Apr 13, 2014
I was actually going to get a ASRock Z170M OC Formula board.

whats the sweet spot for ddr4 then, speed/timings wise.
 

wingman99

Member
Joined
Dec 10, 2003
There are many kits not available in mass sales. It's hard to pick many IC that will run at DDR4-4333 settings. There are other Trident Z which are black/yellow and cost less. On most motherboards you won't be able to set more than ~4133 anyway ( on some not even 3600+ ) and anything past 3733 is way too overpriced.
Personally I recommend Trident Z 3200 CL14/15 or 3600 CL16. Both should run at 4000/1.35V and relaxed timings.

I don't know what motherboard you have but from ASRock only OC Formula runs above 4000 without issues. ASUS has maybe 2-3 boards from ROG series but even Hero/Extreme can't make much more than 4000. From MSI you can find couple models that have guaranteed 4266. I don't know what about Gigabyte but most users have problems with them above 3200-3600.
4333 kit is simply designed for OCFM which has shorter traces than regular boards and is more like ITX board on micro ATX PCB.

What makes boards not able to handle the faster memory speeds It just can't be sub timings or is it?
 

Leegit

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Apr 4, 2013
Location
Kansas
It is mostly the voltage capability of the board + the sub-timings.

When you are transmitting a bit pattern you typically want less than 1 error per billion bits. Running all billion of the bit permutations creates an eye-diagram, the signal must always be outside the eye-mask, which delimits the zone of where fuzzy logic occurs and the receiver can't tell if it is receiving a 0 or 1, in order to be stable. By raising the voltage, you are expanding the eye-diagram and allowing more bits to fall outside the eye-mask, increasing stability. If your timings are too short, the risetime of the signal won't be fast enough to rise to a 1 state or fall to a 0 state and resulting in an undetermined state.
 

EarthDog

Gulper Nozzle Co-Owner
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I was actually going to get a ASRock Z170M OC Formula board.

whats the sweet spot for ddr4 then, speed/timings wise.
DDR4 3000-3200 MHz CL14/15

It is mostly the voltage capability of the board + the sub-timings.

When you are transmitting a bit pattern you typically want less than 1 error per billion bits. Running all billion of the bit permutations creates an eye-diagram, the signal must always be outside the eye-mask, which delimits the zone of where fuzzy logic occurs and the receiver can't tell if it is receiving a 0 or 1, in order to be stable. By raising the voltage, you are expanding the eye-diagram and allowing more bits to fall outside the eye-mask, increasing stability. If your timings are too short, the risetime of the signal won't be fast enough to rise to a 1 state or fall to a 0 state and resulting in an undetermined state.
There is more to it than that... also, the timings come from the XMP profiles on the stick AFAIK. Voltage to the sticks may be a factor, but, most will run u to 1.8V which a lot of DDR4 IC's don't scale too much past that... Im thinking its more in the BIOS and architecture of the board, really.
 

Leegit

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Apr 4, 2013
Location
Kansas
I dunno how much firmware plays into it really. Unless there is some sort of pre-emphasis built-in to the board to compensate for their specific board design.

Each board routes the traces between the memory controller and the DIMMs differently. Increase trace length (dielectric/conductor losses, compensated by more voltage) and reflections from the discontinuities (slower rise-times, compensate with looser sub-timings) will affect the signal integrity too.

For example, speed of light is 300 mm / ns in air and in a board made of FR4 its going to be roughly 150 mm / ns. 4GHz clocks are going to have a rise-time of roughly 0.09 ns. So the spatial extent of the rising/falling edge for the bits will be 13.5 mm. Any impedance discontinuity (turns/bends in trace) of 1/10th that feature size will produce reflections that will degrade the signal. At some point the "eye" in the eye-diagram will close and you will consistently fail to pass the eye-mask which leads to instability.
 

EarthDog

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Firmware plays some role. There are plenty of instances where memory is clocking better with BIOS updates. Not sure why or how though.
 

wingman99

Member
Joined
Dec 10, 2003
I dunno how much firmware plays into it really. Unless there is some sort of pre-emphasis built-in to the board to compensate for their specific board design.

Each board routes the traces between the memory controller and the DIMMs differently. Increase trace length (dielectric/conductor losses, compensated by more voltage) and reflections from the discontinuities (slower rise-times, compensate with looser sub-timings) will affect the signal integrity too.

For example, speed of light is 300 mm / ns in air and in a board made of FR4 its going to be roughly 150 mm / ns. 4GHz clocks are going to have a rise-time of roughly 0.09 ns. So the spatial extent of the rising/falling edge for the bits will be 13.5 mm. Any impedance discontinuity (turns/bends in trace) of 1/10th that feature size will produce reflections that will degrade the signal. At some point the "eye" in the eye-diagram will close and you will consistently fail to pass the eye-mask which leads to instability.

Cool I know what your are saying, so relaxed sub timings with the Bios update is what they do so the data is transfer before the rise and fall of the signal. Increasing the voltage out of intel's calculated speciation's according to path and memory controller will allow the single interference to be less due to a stronger signal and less conducive interference. They also use spread spectrum.
 

Leegit

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Firmware plays some role. There are plenty of instances where memory is clocking better with BIOS updates. Not sure why or how though.

I don't know either :shrug: Updating the pre-emphasis parameters could be one reason though. It's used on the transmitter to alter the waveform outputted from the driver to compensate for the signal degradation introduced by the trace so that by the time it reaches the receiver it is a cleaner signal. It's the equivalent to noise cancelling technology in headphones but on PCBs.
 

Woomack

Benching Team Leader
Joined
Jan 2, 2005
What makes boards not able to handle the faster memory speeds It just can't be sub timings or is it?

Motherboard design. Generally shorter traces = less interference = higher max clock as signal is more stable. You can see that 2 memory slot motherboards like most ITX are overclocking better. One of the cheaper higher series Z170 boards is MSI Z170I Gaming Pro AC which has no issues to run at 4133 and max on the tested memory list is 4266. On this board was world record some time ago and first official DDR4-5000+. ASRock OCFM was made in similar way and it's like ITX length traces with additional stability on micro ATX board.

What also counts and is probably more important is how BIOS is designed. Most motherboards have BIOS tunned for stability, not max overclocking. It doesn't mean that overclocking series boards are less stable. Right now the best memory overclocking boards are OC Formula series from ASRock and higher MSI Gaming and OC boards. All other brands can barely pass 4000. Even highest ROG boards have often issues to pass 3866 stable in dual channel.

Timings depend from board design but also general system stability and OS. This is weird but you can't lower timings too much or Windows won't be able to address it without errors, even though memory can be stable.

On Skylake memory is scalling good up to at least DDR4-3600. However in games etc you won't see special difference above ~3200. Best is to buy good 3200 CL15-15-15 kit and overclock it if you want higher frequency. Trident Z 2x8GB 3200 CL14-14-14 and 15-15-15 are on the best Samsung IC which in most cases can handle 4000-4133 without issues.
 
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wingman99

Member
Joined
Dec 10, 2003
Motherboard design. Generally shorter traces = less interference = higher max clock as signal is more stable. You can see that 2 memory slot motherboards like most ITX are overclocking better. One of the cheaper higher series Z170 boards is MSI Z170I Gaming Pro AC which has no issues to run at 4133 and max on the tested memory list is 4266. On this board was world record some time ago and first official DDR4-5000+. ASRock OCFM was made in similar way and it's like ITX length traces with additional stability on micro ATX board.

What also counts and is probably more important is how BIOS is designed. Most motherboards have BIOS tunned for stability, not max overclocking. It doesn't mean that overclocking series boards are less stable. Right now the best memory overclocking boards are OC Formula series from ASRock and higher MSI Gaming and OC boards. All other brands can barely pass 4000. Even highest ROG boards have often issues to pass 3866 stable in dual channel.

Timings depend from board design but also general system stability and OS. This is weird but you can't lower timings too much or Windows won't be able to address it without errors, even though memory can be stable.

On Skylake memory is scalling good up to at least DDR4-3600. However in games etc you won't see special difference above ~3200. Best is to buy good 3200 CL15-15-15 kit and overclock it if you want higher frequency. Trident Z 2x8GB 3200 CL14-14-14 and 15-15-15 are on the best Samsung IC which in most cases can handle 4000-4133 without issues.

From board to board ATX ITX standard, how do they shorten the tracers when the memory distance from the CPU to memory is the the ATX and ITX standard, memory ATX ITX distance to CPU for the intel cooler?
Also I read Asus has customized trace layout for reduced crosstalk and coupling noise on The Z 170A does it do better than all the other boards on memory overclocking? What do they change in the Bios for better memory overclocking besides VCCIO and VCCSA?:shrug:
 

EarthDog

Gulper Nozzle Co-Owner
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Location
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How many ways can you get the the same place in real life? ;)

The ASUS thing is marketing, just like DDR4 boost from MSI. I am sure it helps, but, many boards have those 'features' and overclocking ram still varies on all of them. As was said by myself and bart, it is a combination of things from hardwiring to the firmware.
 

Woomack

Benching Team Leader
Joined
Jan 2, 2005
MSI Boost is actually working. I had a chance to test it on 3 boards and even the cheapest mATX Mortar can make 3600. Boards with this feature are overclocking better. ASUS thingy is not working so good. Even the best ROG boards can't beat MSI which cost less. Like ROG Impact cost 2x more than MSI Gaming AC while MSI is overclocking better and both are in ITX format.
ITX boards have shorter traces from memory to CPU - there are 2 memory slots. Think that on 4 slot boards first slots which have also traces in straight line to the CPU are not 1/2 but 2/4 counting from CPU side so are maybe 30% longer than on ITX boards. ASRock OCFM has also shorter traces and 2 memory slots. On MSI boards and some other too, the way how traces go is painted on the PCB so you can easier check it.
On many larger boards there are additional components on the way like additional capacitors, resistors, mounting holes etc. The best overclocking motherboards have nothing on the way between memory and CPU. There are Gigabyte LN2 series boards without mounting holes for CPU cooler so traces won't have to go around them.

Also the best memory overclocking X99 motherboard is ASRock X99M Killer 3.1 ... not OCF. It's 4 slot motherboard. There are 2 advantages which I see on this board. One is higher max frequency and other is that in time I see no issues with memory recognizing. For some reason many full ATX X79 and X99 boards have issues with memory slots after longer usage ( especially when you switch memory often ). I'm not sure why but I had that on couple of boards already and some other users were reporting similar issues on the forums. I mean when system sees whole RAM but is working in triple channel or can't see memory in some slots.

BIOS is generally designed for stability or max overclocking. Even if motherboard is in ITX format then it doesn't mean it will overclock good. I had ASRock ITX Gaming something which could run at 3733+ only in single channel. At the end you can see that memory manufacturers are advertising 4000+ memory kits but not many motherboards can actually handle so fast memory. Most of these kits were tested on 5-6 motherboards on the market. Most 4133+ kits were tested only on ASRock OCF and 2-3 higher MSI boards.
 
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Leegit

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Apr 4, 2013
Location
Kansas
From board to board ATX ITX standard, how do they shorten the tracers when the memory distance from the CPU to memory is the the ATX and ITX standard, memory ATX ITX distance to CPU for the intel cooler?
Also I read Asus has customized trace layout for reduced crosstalk and coupling noise on The Z 170A does it do better than all the other boards on memory overclocking? What do they change in the Bios for better memory overclocking besides VCCIO and VCCSA?:shrug:


Crosstalk and coupling noise are the same thing. Crosstalk is energy from one conductor coupling to an adjacent line through mutual inductance and/or mutual capacitance. This always occurs during a rising or falling edge because there is a dI / dt at that moment where the edge is located on the transmission line as it propagates. It is also sometimes referred to as switching noise. Crosstalk comes in two types, near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The only difference being which direction the energy travels after it couples over to the adjacent conductor.

As Woomack pointed it out, even if the length (or time delay) of the conductor (really should be called a transmission line) is constant. There are other effects that cause signal degradation, namely reflections. Any time a signal sees an impedance discontinuity, part of the energy of the signal will reflect off that interface and travel in the backwards direction and the signal travel in the forwards direction will be alterred, so if there are addition resistances, capacitors, inductors, adjacent traces, change in dielectric constant, bends, turns, vias, etc. that will introduce minor reflections which increases the noise in the transmission line and it will get worse as the frequency goes up. This is because as we overclock and raise the frequency, the signal is able to "see" more imperfections in the transmission line. See my previous reply above on spatial extent of the signal.

Another important point is that having less receivers (DIMMs) will result in a higher overclock. The transmitter or driver must be routed to all it's receivers and at the split there is a impedance discontinuity and upon arrival at the receiver, it must be perfectly matched to the characteristic impedance of the transmission line, if its not, you get a reflection off the receiver which travels backwards. So the more branches we have, the more small reflections we expect to be propagating alone the path before they dissipate from the losses of the transmission line.

A quick example is the step from DDR2 to DDR3. The main difference between the two technologies is the routing topology to the receivers. With DDR2, they were using a "star" topology where the signal is split and branches out and then they are individually routed to the receivers. The advantage here is each receiver is the same length (or time-delay) from the transmitter, so the timings of when to expect to read the bits is the same for all receivers. The problem with this are the issues I mentioned above, discontinuity at the split and the reflection from the non-ideal termination at the receiver. The reflections would then propagate backwards and go down the other paths, causing more noise the higher the frequency was raised (impedance of the transmission line is not constant with frequency ;) ).

For DDR3, they switched over to a "daisy-chain" topology, where the transmission line is tapped at different points along the transmission line for each receiver. The advantage is that there is less noise from reflections propagating on the other paths. The disadvantage is that each receiver is a different length (or time-delay) from the transmitter. So the timing for reading a bit is different depending on which receiver is reading it. With some work you can get around that though by adding a built-in offset based on the difference in electrical length (changes with frequency) from the first receiver to receiver n.
 
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wingman99

Member
Joined
Dec 10, 2003
Crosstalk and coupling noise are the same thing. Crosstalk is energy from one conductor coupling to an adjacent line through mutual inductance and/or mutual capacitance. This always occurs during a rising or falling edge because there is a dI / dt at that moment where the edge is located on the transmission line as it propagates. It is also sometimes referred to as switching noise. Crosstalk comes in two types, near-end crosstalk (NEXT) and far-end crosstalk (FEXT). The only difference being which direction the energy travels after it couples over to the adjacent conductor.

As Woomack pointed it out, even if the length (or time delay) of the conductor (really should be called a transmission line) is constant. There are other effects that cause signal degradation, namely reflections. Any time a signal sees an impedance discontinuity, part of the energy of the signal will reflect off that interface and travel in the backwards direction and the signal travel in the forwards direction will be alterred, so if there are addition resistances, capacitors, inductors, adjacent traces, change in dielectric constant, bends, turns, vias, etc. that will introduce minor reflections which increases the noise in the transmission line and it will get worse as the frequency goes up. This is because as we overclock and raise the frequency, the signal is able to "see" more imperfections in the transmission line. See my previous reply above on spatial extent of the signal.

Another important point is that having less receivers (DIMMs) will result in a higher overclock. The transmitter or driver must be routed to all it's receivers and at the split there is a impedance discontinuity and upon arrival at the receiver, it must be perfectly matched to the characteristic impedance of the transmission line, if its not, you get a reflection off the receiver which travels backwards. So the more branches we have, the more small reflections we expect to be propagating alone the path before they dissipate from the losses of the transmission line.

A quick example is the step from DDR2 to DDR3. The main difference between the two technologies is the routing topology to the receivers. With DDR2, they were using a "star" topology where the signal is split and branches out and then they our individually routed to the receivers. The advantage here is each receiver is the same length (or time-delay) from the transmitter, so the timings of when to expect to read the bits is the same for all receivers. The problem with this are the issues I mentioned above, discontinuity at the split and the reflection from the non-ideal termination at the receiver. The reflections would then propagate backwards and go down the other paths, causing more noise the higher the frequency was raised (impedance of the transmission line is not constant with frequency ;) ).

For DDR3, they switched over to a "daisy-chain" topology, where the transmission line is tapped at different points along the transmission line for each receiver. The advantage is that there is less noise from reflections propagating on the other paths. The disadvantage is that each receiver is a different length (or time-delay) from the transmitter. So the timing for reading a bit is different depending on which receiver is reading it. With some work you can get around that though by adding a built-in offset based on the difference in electrical length (changes with frequency) from the first receiver to receiver n.

How do they test or measure reflection off the receiver which travels backwards? You would think there would be a set specification for all motherboards memory tracers with DDR3 or DDR4.
 

Leegit

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Apr 4, 2013
Location
Kansas
How do they test or measure reflection off the receiver which travels backwards? You would think there would be a set specification for all motherboards memory tracers with DDR3 or DDR4.

This is done by using a Vector Network Analyzer (VNA), they come in multiple configurations. Usually 2-port or 4-port, or more. After you calibrate the device, you connect port 1 to the transmitter side and port 2 to the receiver side. The device then sends a series of 1V amplitude sinusoidal waveforms (sine-waves) of different frequencies through the transmission line. As the wave propagates, the VNA detects the energy on port 1 and port 2 being received. This gives you a 2x2 matrix called the scattering parameters. S-parameters. They fully characterize (describe) the behavior of the transmission line over the frequency range you select. It allows you to treat the transmission line as a "black-box", without knowing anything about what is happening inside, you know how the energy flows, in dB.

S11 = stimulus in port 1, response out port 1
S12 = stimulus in port 1, response out port 2
S21 = stimulus in port 2, response out port 1
S22 = stimulus in port 2, response out port 2

Ideally, S11 = S22 and S12 = S21... giving a symmetric transmission line.


The specification is that the receiver impedance should match the characteristic impedance of the transmission line at the operating frequency. However, exact matches are not realistic. Also, when we overclock, we change the frequency and the characteristic impedance of the transmission line will change slightly but the termination at the receiver, usually a discrete resistor, may not change in proportion, so the mismatch will grow larger typically.