The REAL difference between D1 and M0 P4's

[arklab]

From reading recient threads there seems to be a LOT of confusion about just what the differences are between the older D1 steping and newer M0 steppings.
I'm posting this thread to highlight what Intel is saying about them.
I do NOT intend to claim any real knowledge about just how overclockable each is. Check other threads for that.

In a nutshell, any CPU with an M0 stepping is an EE core chip, but obviously having the L3 cache crippled.

I'd susgest going to
http://processorfinder.intel.com/scripts/default.asp

Then first select the EE family and check Sspec's; Then the Pentium 4 family, list all and scan for M0.

They seem to share a new copper heat spreader on the inside of the current integrated heat spreaded.
This seems to be bonded to the die by what is described as "solder" or "epoxy", by those who have sadly tried to remove the heat spreader.
I believe this will also be the standard used in Prescott and Tejas.
Conjecture: Seeing just what a blast-furnace the "real" EE chips are, this may be Intels solution to better cooling with air.

See the article: http://www.vr-zone.com/?i=308&s=1

Intel also states that D1 stepping is NOT being discontinued, 'though packageing will change.

Further conjucture: IMHO the M0's are the result of Intel having lousey yealds on the EE, and this is a way to dump bined CPUs. Therefore, they may disappear as quickly as they have arrived!

OK, thats what I have been able to find.
Some may be WRONG.
And ALL of it was scatered here and there in other threads by other people. They did the really hard work.

Hope this helps and Please feel free to correct anything I've screwed up here!

 

[deathman20]

Hmmm intresting if the D1's arn't being discontinued, maybe thats why only a few M0 stepping chips have made it to the market.

Itresting facts though if it does pan out true. I really hope though the M0's don't go byebye. That would be a sad day for all of us.

 

[Jognt]

woohoo, so my D1 is cool, but them M0's are just failed experiments lol

 

[FIZZ3]

woohoo, so my D1 is cool, but them M0's are just failed experiments lol

The M0's are failed 3.2Ghz EE's, the D1's are failed 3.2Ghz Vanilla's.

 

[ol' man]

The IHS on all CPU's since the PII 233MHz have been nickel coated copper. That VR zone article is kinda stupid in the way they say there is a new copper layer. I doubt it. It is simply a area on the IHS that has not been coated with nickel that is all. This will allow the solder to stick better to the IHS.

 

[Jognt]

the EE's are just "glued" to the die a lot better, so you would rip of the die before getting it loose

The M0's are failed 3.2Ghz EE's, the D1's are failed 3.2Ghz Vanilla's.

aw man, thanks for ruining my fun

 

[FIZZ3]

aw man, thanks for ruining my fun

Haha yes the truth can hurt.

Actually, the D1 stepping may be the better choice because Intel is likely to have more difficulties with getting sufficient 3.2 EE's than with 3.2 Vanilla's. That means that the chance that a D1 is actually a re-binned 3.2 Vanilla is higher than the M0 being a rebinned 3.2 EE. Happy again now?

 

[arklab]

From what I read, there is now an additional slab of copper under the IHS.
According to the Intel product change notice, the overall height is now a little greated. I'd suspect this if there is more copper under the spreader.

I guess the BIG question is:
Did Intel really phisically disable that L3 cache?

Or is it sitting there, waiting, unused, for Abit or Asus or some other mobo maker to sell a LOT of motherboards with just a BIOS change!

And before you say "It CAN"T be", recall the 'PAT-like" mod to i865's Asus started just this year.

That thought ought to get the jucies going.

 

[TC]

This doesn't account for why the actual core of the real EE is noticeably larger than the slower M0 chips.

 

[Jognt]

From what I read, there is now an additional slab of copper under the IHS.
According to the Intel product change notice, the overall height is now a little greated. I'd suspect this if there is more copper under the spreader.

I guess the BIG question is:
Did Intel really phisically disable that L3 cache?

Or is it sitting there, waiting, unused, for Abit or Asus or some other mobo maker to sell a LOT of motherboards with just a BIOS change!

And before you say "It CAN"T be", recall the 'PAT-like" mod to i865's Asus started just this year.

That thought ought to get the jucies going.

that would mean that the L3 cache might be reconnected and thus: used by the CPU, now that would be cool!

Haha yes the truth can hurt.

Actually, the D1 stepping may be the better choice because Intel is likely to have more difficulties with getting sufficient 3.2 EE's than with 3.2 Vanilla's. That means that the chance that a D1 is actually a re-binned 3.2 Vanilla is higher than the M0 being a rebinned 3.2 EE. Happy again now?

sorta

 

[FIZZ3]

I guess the BIG question is:
Did Intel really phisically disable that L3 cache?

Or is it sitting there, waiting, unused, for Abit or Asus or some other mobo maker to sell a LOT of motherboards with just a BIOS change!

And before you say "It CAN"T be", recall the 'PAT-like" mod to i865's Asus started just this year.

"It can't be."

There is a big difference between CPU-based disabled features like the multiplier lock and the Celeron's smaller cache (on a lot of Celly types) and a mainboard based bypass feature like PAT.
Intel is very thorough in its CPU maiming procedures, nothing like the bridge connections on top of AMD chips. The chance that they would leave this cache for the picking is next to nil in my opinion.

 

[NookieN]

The newest D1s and M0s are fairly similar architecturally. I would be inclined to say you're better of trying to get a D1 from a fairly recent week (not the pack date) than an M0

the EE's are just "glued" to the die a lot better, so you would rip of the die before getting it loose

It's not glue or epoxy. The IHS is soldered to the die, which provides better heat transfer than the grease TIM.

I guess the BIG question is:
Did Intel really phisically disable that L3 cache?

Yes, it's fused off. Even if there were a way to enable it, you wouldn't want to do so. A defective cache doesn't exactly help performance.

Originally posted by TC
This doesn't account for why the actual core of the real EE is noticeably larger than the slower M0 chips.

The EE has 2M of L3 of course. But Intel makes 1M Xeon chips too. In theory, M0s could be either 2M or 1M chips where the L3 cache could not be recovered.

 

[arklab]

The thread gets even more interesting.

Yes, it's fused off. Even if there were a way to enable it, you wouldn't want to do so. A defective cache doesn't exactly help performance.

That Intel "blew" the fuses on the cache is quite possible, however I'm not so sure they are able to do so.
So far the fuse lock system has been used on the A) multiplier, B) HyperThreading, and C) L2 cache. All these were forseeable when the P4 was first being designed, and so were incorporated into the design from the very begining.

Here, however, we are looking at L3 cache.
Frankly I don't think Intel ever considered adding this to the P4 design. I feel this was rather done in some haste as a PR response to AMD's Hammer CPU's which looked threatening at the time.
Weather the EE is a quickly improved P4 or a Zeon with a different pin package doesn't really matter.
In ether case the EE wasn't a forseeable event, and therfore not as likely to have "fuses" built in to disable the L3.

Further, if the M0's are more a flash-in-the-pan CPU that will disapear in a month or two (VERY likely, since the D1's are to continue production) it's not really even an economic threat to Intel.

If the chips were bined due to defective L3, than you may be right.
But we don't know that this is the case.
They may simply not been able to pass at 3.2G with the margin of safety Intel requires of it's EE's, and could run just fine at 2.4 or 2.8.

The big question is still if Asus or Abit or whoever will alter the BIOS to permit L3 (if present) to be turned ON.

A BIOS hack might also at least answer the question.

 

[NookieN]

Here, however, we are looking at L3 cache.
Frankly I don't think Intel ever considered adding this to the P4 design. I feel this was rather done in some haste as a PR response to AMD's Hammer CPU's which looked threatening at the time.
Weather the EE is a quickly improved P4 or a Zeon with a different pin package doesn't really matter.
In ether case the EE wasn't a forseeable event, and therfore not as likely to have "fuses" built in to disable the L3.

That's not the case though. The EE isn't something that Intel just threw together at the last minute. It is basically a 2M Xeon die (aka Gallatin) that is being repackaged as a desktop part. The Xeons of course have programmable fuses just like the mainstream P4s.

And pretty much any modern cache design requires fuses to handle the redundancy -- the extra lines of cache that can be switched in to replace defective ones. When fusing is implemented for cache redundancy, adding a fuse to simply disable the cache would be a trivial matter.

If the chips were bined due to defective L3, than you may be right.
But we don't know that this is the case.
They may simply not been able to pass at 3.2G with the margin of safety Intel requires of it's EE's, and could run just fine at 2.4 or 2.8.

Intel still sells 2Ghz, 2.5Ghz, and 2.8Ghz Xeon MPs with L3 cache. Those chips command a hefty premium, so I very much doubt that they would sell these as sub-$200 chips if they still worked as $2000 chips.

 

[arklab]

Some good points, NookieN.
And you may well be right.

However, the matter has yet to be put to the proof.

I'm sure you recall all the articles (and ALL by experts) on the introduction of the i865 chipset that NO PAT was available.
Intel was CERTAIN that was the case.

Untill Asus.

The vampires greatest weapon is that no one believes they exist.

Just produce a BIOS that supports L3 with a 2.4G, turn it ON, and show no change in Sandra.

Then you will have PROVED your point.

Till then were BOTH just blowing smoke.

 

[FIZZ3]

Just produce a BIOS that supports L3 with a 2.4G, turn it ON, and show no change in Sandra.

Ok, I'll try one more time to make this clear: there is NO way that a mainboard/BIOS setting can change something that is physically locked and NOT accessible and that is on the CPU. It's simply nothing like the PAT enable, which was 100% mainboard based.

Optimism and an open mind are good things, but you're taking it well into wishful thinking territory. The reality is that it will not work like that.

 

[Jimbob7]

Ok, I'll try one more time to make this clear: there is NO way that a mainboard/BIOS setting can change something that is physically locked and NOT accessible and that is on the CPU. It's simply nothing like the PAT enable, which was 100% mainboard based.

Optimism and an open mind are good things, but you're taking it well into wishful thinking territory. The reality is that it will not work like that.

I agree. Do you really think that intel would release a clocked down 3.2 ee with L3 cache disabled which are selling at about 130 pounds against the 3.2 ee which are about 600 pounds, that you can then overclock to 3.2 or more AND enable the L3 cache saving you almost 500 pounds.... hehehe

 

[arklab]

Ok, I'll try one more time to make this clear: there is NO way that a mainboard/BIOS setting can change something that is physically locked and NOT accessible and that is on the CPU. It's simply nothing like the PAT enable, which was 100% mainboard based.

OK, please show me the thread where someone has PROVED that the L3 is LOCKED OUT.

It prob. IS, but you are jumping to a conclusion just as fast as I am.

I agree. Do you really think that intel would release a clocked down 3.2 ee with L3 cache disabled which are selling at about 130 pounds against the 3.2 ee which are about 600 pounds, that you can then overclock to 3.2 or more AND enable the L3 cache saving you almost 500 pounds....

Intentionally, NO.

My point is (so far) nobody really knows, now do they?

I hope is that someone with the resqusite skills gives it a try.

Unlocking HT on early P4's proved frutless.
But at least people TRIED!

As a result , now we know it dosen't work.

 

[Jimbob7]

But what i stated is that its HIGHLY UNLIKEY that you can re enable the L3 cache, and if you can, that would be lazyness or stupidity ( which i doubt ) from intel. Although i understand what you are saying that there could be a slight chance therefore we must try.

 

[FIZZ3]

OK, please show me the thread where someone has PROVED that the L3 is LOCKED OUT.

It prob. IS, but you are jumping to a conclusion just as fast as I am.

I am not. You refuse to acknowledge the information you've been given in this thread that points strongly in the direction that I've argued.

Trying to cloud the issue by claiming something has not been "proven" is weak IMO. You're saying that black swans exist, and not accepting any observations about thousands of white swans that are observed by yelling "you have not observed ALL swans yet!"

This thread is about information that can only be obtained by inference (at this point). Why ask for inferences and then not acknowledge them?