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Euclid][CID][

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Hey,

I'm runing an Abit KR7A-Raid with an Athlong XP 1700+ @ 1663 MHz. I can't seem to raise the FSB any higher than 140 or so, and cooling doesn't seem to be the problem. I'm pretty sure that it is the voltage. The mobo won't let me go about 1.85v. I need a reliable site that describes how to mod my mobo to gain more power! Thanks.
 
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Euclid][CID][

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Thanks, but...

To tell you the truth, I'm a little frightened by the idea of soldering on my motherboard. I get shaky hands when I try to do small-scale, precision tasks (you shoulda seen me trying to make sure my tape was lined up right etc. when I was OCing my XP heh). Anyway, I was wondering if there is any way to do it w/out soldering. If not I'll just have to hold my breath and do it, but if there is I'd sure like to try that first! Thanks.
 
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Euclid][CID][

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Curious

Okay,

So I'm absolutely LOVING my new unlocked XP processor. I was frightened when I did it, but I am so glad I did. I'm gonna work on the voltage mods and cooling, but I have another question for you.

I've been noticing that a lot of people are running with a FSB of 140+. When I set mine above 139 (which SiSoft Sandra recognizes as 140 for some reason) I get an error when trying to boot into Windows XP Pro. It tells me that there is an error in the config file and that I can repair it using the windows recovery console. Does anyone know what is going on?

Also, I have trouble with my AGP and PCI settings. The BIOS only supports setting ratios or 4:2:1 and 3:2:1 (I fail to see the point of a 3:2:1, but whatever). I read in Paul's FAQ about the mobo automatically setting it to 1/5 etc. but I have yet to see this happen. Could anyone shed some more light on the subject.

Also, sonny, I wanted to thank you for spending time answering my posts. Thanks!

Euclid
 

Sonny

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When you have problems with the FSB your going to need to learn about a few basic facts about memory settings here are some of the basics;

A short intro to SDRAM, penalty cycles and latencies

SDRAM (same as DDR) is not infinitely fast. DRAM consists of capacitors, gating transistors and bit lines and worldliness (data lines and address lines). Capacitors and lines need to be precharged and the address strobes need time to lock into the correct position in order to retrieve the data.

1. The typical cycle starts with a bank activate command that selects and activates one bank and row of memory through the input pins.

2. During the next cycle, the data is selected onto the data (or bit) lines and moves towards the sense amplifiers.

3. When the data bits reach the sense amplifiers the data is latched by an internal timing signal.

4. This process takes length of time called the Row Access Strobe to Column Access Strobe delay (RAS to CAS delay) with a latency of usually two or three cycles.

5. After this delay, a read command can be issued along with the column address to select the address of the first word to be read from the sense amplifiers.

6. After the read command there is a CAS delay or latency while the data is select from the sense amplifiers and clocked to the output pin. The CAS latency is typically 2 or 3 cycles. Once the data is released to the bus, another word is output every cycle until the data burst is complete.

7. Only after all the information has been output, the data can be moved back from the sense amplifiers to the row of cells to restore its contents. Movement of the data back to the empty cells again takes 2 to 3 clock cycles.

8. Depending on the leaking or bleeding of the memory cells, the quality of the charge may have to be restored during a so-called refresh cycle. The need for a recharge is determined by a refresh controller whereas the actual process of refreshing is monitored by the refresh counter. This refreshing requires additional 7-10 clock cycles during which the data flow is interrupted and, thus results in a performance hit.


The typical timing settings that decide over performance are:

SDRAM CAS Latency, CAS-DL; often called DRAM cycle time:(n cycles) number of cycles the column address strobe needs to select the correct address.

SDRAM tRAS-to-CAS Delay, tRCD; often described as Bank X/Y DRAM timing:(n cycles) number of cycles from when a bank activate command is issued until a read or write command is accepted, that is, before the CAS becomes active. In other words, after a bank activate command, the RAS lines need to be precharged before a read command (specifying the column address) can be issued. This means that the data need to be moved out of the memory cells into the sense amps which takes somewhere between 2 and 3 penalty cycles. It is important to know that tRCD only plays a minor role in the overall penalty since most reads occur as page hits, data are read out of a page already open (but see below). Unfortunately, in most BIOS, tRCD is not directly accessible, at least not under its real name but is hidden in the Bank X/Y DRAM Timing field.

SDRAM SRAS Precharge Delay: tRP (n cycles) necessary to move the data back to the cell of origin (close the bank / page) before the next bank activate command can be issued.

The weighting of different latencies

Somewhere between 30 and 60% of all read requests fall within the same page (or row) which is called a page hit. In this case, there is no need for the bank activate and tRCD, the data are already in page and the only thing that needs changing is the column address via the Column Address Strobe. Therefore, the CAS-latency becomes the most important factor in the performance of the main memory subsystem.

If the data requested are not found within the same page, the data need to be moved back to the memory cells and the bank will be closed. There are two different cases to be considered.

a. Either, the data are located in the same bank but in a different row, in this case, a precharge command needs to be issued, the bank will be closed within two or three cycles (tRP) and a new bank activate command will open the correct row (tRCD). Subsequently, a read command will select the correct column address (CAS delay). In this case, the full number of penalty cycles for CAS-DL, RAS-to-CAS and precharge will pass until the next data are output. In the case of a 2:2:2 DIMM, this will mean 6 penalty cycles, with a 3:3:3 part, the latency will increase to 9 cycles.

b. If the requested data are located in a different row, it is not necessary to wait for the first bank to close and, thus, tRP can be skipped. Consequently, the latency only comprises tRCD and CAS-DL. Precharging of the first bank (closing the page) can then occur in the background of RAS-to-CAS delay of the second bank.


It does get a bit more complicated than that. If data are contained within the same bank but in a different row, the bank needs to be closed and reactivated. In this case, the bank cycle time SDRAM tRC becomes a critical factor since every bank has a minimum time that it needs to stay open.

Bank cycle time tRC (SDRAM active to precharge time), tRAS

[5T, 7T], [7T ,9T] (Intel i815 chipset)
[5T, 7-8T], [6T ,8-9T] (VIA chipsets)
[3-10T, 4-15T] ALiMAGiK1 chipset

The bank cycle time (tRAS) specifies the number of clock cycles needed after a bank active command before a precharge can occur. In other words, after a page has been opened, it needs to stay open a minimum amount of time before it can be closed again. tRC specifies the minimum cycle time until the same bank can be reactivated. Since a precharge has a latency of 2 or 3 cycles, Trc is the sum of tRAS and RAS precharge time (tRP). The Intel i815 chipset allows for 5T,7T and 7T,9T, that is, 7 or 9 cycles bank cycle time, that is, tRP is fixed to 2T. The VIA chipsets offer tRAS values of 5T and 6T and allows to set tRP to 2 and 3 cycles, respectively but they are generally not directly accessible but part of a coctail of settings.

Most current high-end SDRAM is specified at about 50-60 ns cycle time. In turn, this means that, theoretically, at up to 133 MHz (7.5ns clock cycle), it is possible to run at a Trc of 7T (7x7.5ns=52 ns). If the clock frequency is increased, the number of cycles has to be increased, too, in order to provide the 50 ns. In other words, the theoretical limitation of the memory speed is somewhere around 183 MHz (9x6ns = 49.2ns). Interestingly, in the early revisions of the i815 chipset boards the bank cycle times were specified as [5T, 7T] and [6T, 8T] which would limit the memory bus to approximately 166 MHz.

For 100 MHz memory bus speed, in order to get best performance, the bank cycle time should be set to 5/7, for the 133 MHz memory bus, it needs to be set to 5/8 or else to 6/8, depending on how much overclocking is involved.

Why is there a minimum bank cycle time and what is tRAS violation?

After the RAS activates a bank, the data are latched onto the sense amplifiers. The way of how that works is that you have two lines, bitlines and bitlines running in parallel where one of them is the signal and the other is the reference. This is not hardwired but works like line interleaving where each line can be the signal and the other one is the reference.

The sense amplifiers sense the voltage differential (the charge released by the memory cell / capacitor onto one bitline) between the charged bitline and the reference bitline and amplify it. This signal can be relatively weak but at the same time it also needs to be restored in the memory cell. This requires amplifying the signal a bit more (up to ca. 2 V). The bitlines themselves have a certain capacitance which slows down the charging up (on average around 30-40 ns).

If a precharge occurs (to wipe all the information from the bitlines for the next bank activate (row access)), before the signal is strong enough to restore the original content in the memory cell, "tRAS is violated", resulting in loss or corruption of the data.

In other words, tRAS is the time necessary to develop the full charge of the bitlines and restore the data in the memory cells before a precharge can occur. A precharge is the command that closes the page or bank, and therefore tRAS is also defined as the minimum page open time. If you add the precharge (tRP) you end up with the total number of clocks required for opening and closing a bank, in other words the bank cycle time or tRC.

SDRAM PH limit

Refreshing is, at present, an almost negligible factor (less than 1% performance hit), however, as explained above, with increasing DIMM density, refreshing will increasingly gain importance. As mentioned above, the need for refreshing originates in the fact that capacitors lose charge and, thus, the information will expire after a certain time. The same paradigm applies to an open page since the sense amps can hold the high or low (I or O) of the information only for a limited time. In order to maintain integrity of the data, because they also have to be restored to the original memory cells, it is necessary to limit the open-time of a page. Some chipsets (BIOS) offer the option of setting the page hit limit (PH-limit), in the case of the original AMD 751 Irongate North Bridge, this limit can be selected between 8 and 64 page hits before mandatory closing of the page.

SDRAM idle cycle limit

Some BIOS interfaces offer the selection of specifying the SDRAM idle cycle limit. This means that an equivalent to the bank cycle time applies to a bank, even when it is idle. Typical settings range from 0 to 8 cycles.

Bank interleaving

One case not mentioned above was hopping from one bank to another when the respective pages are already open on each bank. This is a trick that requires high locality of the data stored in the system memory. Basically, a bank activate command can open one bank at the time and then the readout will occur after tRCD and CAS-DL. However, simultaneously, the memory controller can issue another bank activate command in the cycle after the first command was issued and, thus open the next bank. If the controller knows that the next set of data is going to be in a different bank, it can issue read commands to the next location without trashing the first bank's data burst. This way, there is the possibility to hop from one bank to another with only one penalty cycle (bank-to-bank latency) between four word bursts. In addition, precharge and bank closing can run in the background of readouts from alternating banks. Settings supported are:

a. No interleaving
b. 2-way interleaving (data are toggled between 2 banks)
c. 4 way interleaving (data are toggled between 4 banks)

As nice as this sounds, there are only specific applications that may take advantage of this feature. Specifically, any application heavily depending on the CPU cache will not be able to benefit from 2-way or 4-way interleaving, for the simple reason that the page may have expired by the time the data from the cache are exhausted. In this case, bank interleaving may even cause a performance hit since a wrong bank may be open and must be closed before the next data access.

Give it a serious read & it'll help you out.
 

Sonny

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1. What kind of RAM do you have?
2. What are the memory timings that you currently run?
3. What voltage do you have the memory at?

The MoBo does not have a 1/5 divisor. Let's not argue with that. When you start pushing the FSB your other components will need to be able to tolerate the increased bus speeds & if your HDD isnt cooperating with you then you can get similar errors to what you have now. When I was pushing my FSB there were more than a few times that all my data got corrupted big time & I had to do a clean reainstall of the OS.
 
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Euclid][CID][

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I have Mushkin High-Perf DDR Here is a link to it...

http://www.mushkin.com/cgi-bin/Mush...9e1ce06a24273fc0a8010206bb+EN/products/990856

I run it at CAS 2 as set in the BIOS. Im given the option of running it at 2 or 2.5. That's the only option I've changed. I'm at school right now..so I don't have access to my complete information. I'll post that later today.

If there is no 1/5 divisor...how do you deal with getting your AGP and PCI to run correct at FSB speeds over 140. From what I've read AGP @ over 70ish MHz and PCI @ over 35ish MHz will botch everything up. How do you get around this?! Thanks for your help again.

Hopefully one day I'll be able to answer other people's posts like you've done for me. Thanks.

Euclid
 

Sonny

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You need quality components & it looks like you have really good memory. You migh just need to set it a certain way. Most PCI devices can go 40MHz & AGP to 80MHz. If you do a search a lot of people have hit 180+FSB with your MoBo. There is also an ongoing mystery with the KT266A supporting 1/5 & even 1/6 divisors ifit has the right clock generator. There are tests on the main site proving that there isn't one though.
 
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Euclid][CID][

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PCI and AGP bus.

Here is the section from Paul's Unofficial FAQ regarding the AGP and PCI busses.

"KR7A-RAID-
Yes, although the Realtek-RTM560-266R clock generator that’s used on the KR7A-RAID can change the multiplier as the FSB increases to try to keep the PCI bus speed near the 33MHz. At 166, 200 and 233MHz the clock generator automatically adapts the dividers for AGP and PCI Bus to 1/5, 1/6 and 1/7 for PCI Bus, 2/5, 1/3 and 2/7 for AGP Bus (see here for details). "

That might have something do to with it. Anyway. I did some math based on your packet and at a FSB of 166 it makes my computer run @ about 5.99 ns. This means to be @ 55 ns for the RAM it needs to be running @ 9T I think. Does this seem right and how the heck do I get it to run @ that?

Thanks again for your help.
 

Sonny

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Re: PCI and AGP bus.

Euclid][CID][ said:
Here is the section from Paul's Unofficial FAQ regarding the AGP and PCI busses.

"KR7A-RAID-
Yes, although the Realtek-RTM560-266R clock generator that’s used on the KR7A-RAID can change the multiplier as the FSB increases to try to keep the PCI bus speed near the 33MHz. At 166, 200 and 233MHz the clock generator automatically adapts the dividers for AGP and PCI Bus to 1/5, 1/6 and 1/7 for PCI Bus, 2/5, 1/3 and 2/7 for AGP Bus (see here for details). "
KR7A-/133/RAID Has no 1/5 or higher divisor. Yes I am familiar with PAUL's FAQ but in the link I have just posted the PCI was checked on the slots themselves & did not show any proof of higher divisors. It really boils down to what you want to believe in. I like the ones that show a real test instead of clockgen specs.

What are your settings?
 
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Euclid][CID][

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Clarification

Thanks for clarifying the PCI argument for me. This however leaves one to wonder..how does someone use a FSB of 180+ which whould lead to a PCI bus of 45+?

Anyway, what do you mean by specs? That is, what exactly do you want to know?

Euclid
 

Sonny

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Yeah 45MHz PCI bus speeds are high. From what I have seen here soundcards like the SBLive!/Creative cards only start to crap out at 46+MHz meaning they were hitting 185MHz/370FSB when they started to inhibit FSB overclocking. Quality components is all I can think of.

What I meant by Clock Gen SPECS in that sentence was that even if the tech papers showed that it would kick in the supposed 1/5 divisor at a certain FSB it's another thing if the chipset will run it.
 
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Euclid][CID][

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My mistake

I put specs, you put settings. My bad. I was referring to this...

What are your settings?

And I agree wholly with you about the quality parts. :D That's why in the beginning I went the extra mile and got High Performance RAM. Thanks.

Euclid
 
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Euclid][CID][

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Settings

Here they are.

Soft Menu III
CPU Operating Speed.....................User Define
- CPU FSB Clock (MHz)....................138
- Ratio (FSB:AGP:pCI).....................4:2:1
- Multiplier Setting..........................x12
- Speed Error Hold..........................Diabled

CPU Power Supply.........................User Define
- Core Voltage...............................1.850
- I/O Voltage..................................3.60
- DDR Voltage................................2.85
DQ Control.....................................Center DQ
CPU Fast Command Decode..........Normal

Advanced Chipset Features
AGP
AGP Aperature Size.......................256 MB
AGP Mode......................................4x
Driving Control...............................Auto
Driving Vaue..................................DA**
][All other values are Disabled][

PCI
][All values enabled with the exception of PCI Delay Transactions

DDR
Current FSB Frequency...............133 MHz**
Current DRAM Frequency............133 MHz**
DRAM Clock.................................by SPD
DRAM Timing...............................Manual
CAS Latency...............................2
Bank Interleave..........................Disabled
Precharge to Active (Trp)............3T
Active to Precharge (Tras)...........6T
Active to CMD (Tred)....................3T
DDR DQS Input Delay..................Auto
DDR DQS Input Value..................09**
DDR DQS Output Delay................Auto
DDR DQS Output Value................40**
Command Drive Strenght.............Lo
DRAM Queue depth......................4 Level
DRAM Command Rate...................2T Command
Feedblack Delay...........................Auto


That's all of them. I was reading in another thread that the Vcore might help out the FSB. Thanks.

Eucld
 

Sonny

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Re: Settings

Soft Menu III
CPU Operating Speed.....................User Define
- CPU FSB Clock (MHz)....................138
- Ratio (FSB:AGP:pCI).....................4:2:1
- Multiplier Setting..........................x12
- Speed Error Hold..........................Diabled

CPU Power Supply.........................User Define
- Core Voltage...............................1.850
- I/O Voltage..................................3.60
- DDR Voltage................................2.85 How come your sig says 2.65? PSU issues?
DQ Control.....................................Center DQ
CPU Fast Command Decode..........Normal FAST

Advanced Chipset Features
AGP
AGP Aperature Size.......................256 MB Do you really need that much? Try 64Mb, it should be more than enough
AGP Mode......................................4x
Driving Control...............................Auto
Driving Vaue..................................DA**

DDR
Current FSB Frequency...............133 MHz**
Current DRAM Frequency............133 MHz**
DRAM Clock.................................by SPD
DRAM Timing...............................Manual
CAS Latency...............................2 Try the slowest possible, 3
Bank Interleave..........................Disabled Enabled Will probably limit FSB but keep it on. Better overall performance
Precharge to Active (Trp)............3T Try the slowest possible
Active to Precharge (Tras)...........6T Try the slowest possible
Active to CMD (Tred)....................3T Try the slowest possible
DDR DQS Input Delay..................Auto
DDR DQS Input Value..................09**
DDR DQS Output Delay................Auto
DDR DQS Output Value................40**
Command Drive Strenght.............Lo
DRAM Queue depth......................4 Level
DRAM Command Rate...................2T Command Try the slowest possible
Feedblack Delay...........................Auto

If you want to find out if you have terrible ram all you have to do is use the lowest Multiplier the crank the FSB. You should be below your default clockspeed so the CPU will not be an issue. If it fails to run stable then you got a bum stick of ram or two.
 
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Euclid][CID][

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Okay...

Okay, I'll give this a shot. Hopefully things will work out! Thanks for all your help.

I was looking through another Thread about FSB ratings on the KR7A, and a lot of the people were reaching 154+. I NEED to at least break 145! Anyway....later on.

Euclid