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DDR was a major step forward in the memory industry, however will we ever see something that can read and write 4 times per clock cycle?
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not if they get Quad Damage!!DayUSeX said:SiS is supposed to have a quad channel rambus chipset almost near completion. Would be sweet but rambus is dead as it seems
itizme said:
not if they get Quad Damage!!
Jognt said:
been playing a tad to much Quake m8?
i wish QDR would happen, but as IMOG said, i dont know how they would want to send 2 signals per clock cycle tbh...
stamasd said:Swapping and inefficient use of memory is not the fault of memory chips, it's the fault of the operating system. There's nothing a memory manufacturer can do if Windows is a memory hog.
They could do like the P4 bus and use 2 out-of-phase clocks, and transfer twice for each cycle of those...IMOG said:I don't really know but I would guess no... Single data rate ram only transfered on one side of each wave, while double data rate transfers on both sides. That seems like a logical progression since one side of the cycle was going unused and other hardware could now utilize the extra bandwidth available.
From my understanding of the way things work, I don't see how writing more than twice per clock cycle would be possible.
itizme said:
shhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh, don't tell anyone