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They could do like the P4 bus and use 2 out-of-phase clocks, and transfer twice for each cycle of those...IMOG said:I don't really know but I would guess no... Single data rate ram only transfered on one side of each wave, while double data rate transfers on both sides. That seems like a logical progression since one side of the cycle was going unused and other hardware could now utilize the extra bandwidth available.
From my understanding of the way things work, I don't see how writing more than twice per clock cycle would be possible.