Getting On The Right Bus

DDR2 will be delayed for about a year, or so the Inquirer says.

What does that mean? It’s no big deal to those who can provide true dual DDR systems. It hurts those who can’t.

That’s good news for Intel and bad news for AMD.

Intel: All Set

Intel decided a long time ago that dual-DDR whatever was the way to go. The initial decision was made to suit RDRAM, but suits dual DDR just fine.

Intel’s Springfield and Canterwood chipsets will be able to handle an 800MHz FSB, which means a maximum 6.4Gb worth of bandwidth. That should yield Sandra memory scores north of 4500, and depending how well it scales with increased frequency, could approach 5000.

That’s a very nice boost over to 3300 or so you can get from RDRAM systems, and should tide Intel over nicely until DDR2 does show up. So long as 533MHz DDR2 shows up by the end of 2004, that won’t cramp Intel’s roadmaps at all.

AMD: The EV6 Anchor

AMD faces a much different situation. The Athlon is married to the EV6 bus, and she’s old.

The EV6 bus allows for double-pumping, which means sends two signals per clock cycle. The PIV bus allows for quad-pumping, which means sending four signals per clock cycle.

What that effectively means is that it would take a 400MHz FSB on the EV6 bus to equal a 200MHz FSB on the PIV bus. We aren’t ever going to see a 400MHz FSB on an EV6 bus.

Double-pumping limits in other ways, too. It also precludes effective dual DDR systems using an EV6 bus.

DDR naturally dual-pumps, so it very nicely pumps right into the dual-pumped EV6 bus.

If you have two dual-pumps going, though, you have a big problem. The dual memory is generating four signals per clock cycle, and the bus can only handle two.

It’s like pumping four gallons of water a minute into a pipe that can only handle two. You might get a little more water through when one of the pump isn’t quite delivering two gallons a minute, but that really doesn’t do you much good compared to have a pipe that can handle four gallons of water a minute. That’s why the nForce boards don’t have much to show for dual sticks of DDR. It’s not nVidia; it’s the EV6 bus.

In contrast, the PIV bus gives you a wider pipe that is meant to handle four pumps per whatever rather than two. If you have two pumps pumping two at a time, you may need to play with pump timing a bit, but the pipe can handle all the water.

To quicken the EV6 dual-pipe, you need to get the pumper pumping more water and the pipe able to handle it. DDR2 would be a faster pumper. No DDR2, no faster pumping.

So no DDR2 soon means that memory bandwidth on Athlon systems don’t even stand a chance of staying close to dual-channel DDR PIV systems.

This isn’t the greatest tragedy of all time. Unlike increasing CPU speed, increasing memory speed gets you relatively little actual performance benefit (and no, memory benchmarks aren’t real applications).

Increase CPU speed 50%, and system performance jumps 30-35%. Increase memory bandwidth 50%, and on the whole, you’ll see less than a 10% overall improvment in system performance. Maybe you’ll get around 15% if you use a program/game that can take real advantage of it.

So this is not a performance killer in the real world, just an anchor.

Page 2: What About Hammer?…


(This was revised 2/4/03 to correct an error about connection between Hammer and memory. The original article said that the interconnection between memory and the CPU was a Hypertransport link. While that’s generally true in Hammer systems, memory has its own separate link. I apologize for the error.)

What About Hammer?

Hammer has its own DDR problems, too.

Most of the performance increase with Hammer comes from its onboard memory controller. This bypasses the motherboard’s north bridge and reduces memory latency. For real world today-and-tomorrow work, it’s easily its best feature.

The problem is that this memory controller comes at a heavy price, in two ways.

A direct connection to the memory channels means Hammer must provide a pin on the CPU interface for each and every memory pin. That effectively means 72 pins for each memory connection. In the case of dual DDR, that would mean 144 pins.

As of now, socket 754 provides for only one memory channel, and socket 940 provides for two. It is unclear whether or not AMD even could make provision for a second memory channel within socket 754 (though you can’t consider a nonexistent socket for a nonexistent processor to be a killer constraint)

Presuming socket 754 can’t accommodate another 72 pins for another memory channel, that means socket 754 processors can’t ever have dual DDR (and continue to use the memory controller, at least).

On top of that, the Hammer memory controller is awfully picky. It doesn’t handle whatever you give it, you give it whatever it wants.

In a non-Hammer system, handling new kinds of memory is basically a motherboard problem; if it can’t handle new memory, get a new motherboard that can.

In a Hammer system, handling new kinds of memory is basically a CPU problem; if it can’t handle new memory, you have to get a new Hammer, presuming there’s even a new Hammer to be had.

Yes, there’s been talk of building motherboards with the necessary circuitry to allow one to disable Hammer’s on-board memory controller, but you end up also disabling its main advantage in the process.

Is It Door Number One . . . ?

The delay in DDR2 means that AMD will probably have a .09 micron Hammers out a few months before DDR2 becomes commonly available.

Had DDR2 not been delayed, AMD could have probably picked Door Number Two with little to no problem. Now it can’t, not even for its “new” Hammer.

So, someday, one of these days, we’ll see a Hammer. What will we see?

Door Number One: The memory controller handles just DDR-I.

Door Number Two: The memory controller handles just DDR2.

Door Number Three: The memory controller handles both.

If AMD doesn’t pick Door Number Three (and it’s uncertain if they even can); it’s going to have a big problem selling early Hammers, at least to this audience. If it picks Door Number One, can you say “quick obsolescence?” If it picks Door Number Two, can you say “Where’s the RAM?”

Are you going to want to hear, “Don’t worry, you can make it work by diabling the main performance feature you bought it for?”

Or do you wait until the Hammer is up to speed with DDR2 (and what if it only likes some speeds of DDR2 and not others)?

What door will AMD pick? If they pick the wrong one, they lose you, the informed customer.


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