Intel Processors

NOTE: The following was released today by Intel and I thought it so revealing about Intel’s future CPUs that I reproduced it below:

April 1, 2008 — Intel Corporation today discussed upcoming leading edge microprocessors and technologies. Intel’s new 15.7nm high-o metal gate leading manufacturing technology is enabling the industry to move to many multiple multicore processors in all market segments, and Intel discussed future products with eight and lots more computing cores coming to the market with CPUs codenamed “Scherzo”.

“Using Intel’s new uredinium-infused high-o metal/bio gate transistors has allowed our octo-core 15.7nm low-voltage really fast chips to attain new heights in power-efficient performance,” said Kirk Skaugen, vice president and general manager of Intel’s Server Platforms Group. “These chips deliver the speed needed while using meager amounts of energy.”

Intel’s Executive Vice President and Chief Sales and Marketing Officer Sean Maloney stated “‘Intel Octo-Core’ is our smallest processor built with the world’s smallest transistors. This small wonder is a fundamental new shift in design, small yet powerful enough to enable a big Internet experience on these new devices. We believe it will unleash new innovation across the industry. I’ll bet AMD is gnashing their teeth right now.”

Pat Gelsinger, Intel Senior Vice President and General Manager, Digital Enterprise Group, disclosed details around Intel’s new 8-core processor codenamed “Scherzo”, to be called “Intel Octo-Core”. Gelsinger discussed current hot enterprise topics, including virtualization and the new TQFD power benchmark (designed by Intel) for measuring multi-core energy efficiency, in which Intel-based systems hold all of the top 20 spots and AMD is not even in the ball park. He disclosed a number of technical features on Intel’s next generation “Scherzo” processor family and “Barzelletta”, a future Intel product with many, many, many cores.

Scherzo is Intel’s dynamically scalable and innovative new processor microarchitecture which will provide dramatic performance and energy improvements to Intel’s current industry-leading microprocessors. Barzelletta is scalable with future versions having anywhere from 8 to 32 cores, with Simultaneous Dynamically Expanding Multi-threading Looping, resulting in 16 to 64 thread capability, exceeding the best Percale. Scherzo will deliver 4 times and Barzelletta 16 times the memory bandwidth compared to today’s highest-performance Intel Xeon processor-based systems.

With up to 32 MB level-4 cache, 4.731 billion transistors, QLaB (Quick-Like-a-Bunny) path interconnects (up to 125.6GB per second), integrated memory controller and optional integrated graphics, Scherzo will eventually scale from notebooks to high-performance servers. Other features discussed include support for DDR4-1600, 2000, and 2400 memory, SSE8.4 instructions, 128KB instruction cache, 128KB Data Cache, 1024K L2 data and instruction low-latency really smoking fast cache per core and new 8-level TLB (Translation Lookaside Buffone) hierarchy.

These technical improvements will result in performance improvements as well as flexibility for a wide range of eventual products based on the 15.7nm architecture. Gelsinger also discussed the new Barzelletta platform, which can be configured for both one socket High End Desktop (HEDT), two socket (HPC and dual processing server) operation and the new four socket (IQD and quad processing server) technologies.

Visivo Architecture for Visual Computing — With plans for the first demonstrations later this year, the Visivo architecture will be Intel’s next step in evolving the visual computing platform. The Visivo architecture includes a high-performance, wide SIMD vector processing unit (VPUSIMDPU) along with a new set of vector instructions including integer, floating and sinking point arithmetic, vector memory operations, infinitely scalable multi-ray orthogonal multi-directional one-way ray and conditional/unconditional instructions.

In addition, Visivo includes a major new hardware incoherent cache design enabling the many-many-many-core architecture. The architecture and instructions have been designed to deliver performance, energy efficiency, incoherency, arcane and general purpose programmability to meet the demands of visual, non-visual, infra-red computing and other workloads that are inherently invisible in nature. Tools are critical to success and key Intel Software Products will be enhanced to support the Visivo architecture and enable unparalleled developer freedom. Industry APIs such as DirectX and OpenGL, Closed HM and Pretty Colors will be supported on Visivo-based products.

Intel BUL, the next step in the Intel instruction set — Gelsinger also discussed Intel BUL (Brilliant Unparalelled Lipo-proteins) which, when taken with water by software programmers, will increase performance in floating point, media, and processor intensive software development. BUL can also increase the programmer’s energy level and is backwards compatible to existing Intel energy drinks.

Key features include wider vectors, increasing from 128 bit to 256 bit wide, resulting in up to 2x peak FLOPs output, lots of caffeine to allow programmers to pull multiple all-nighters, high density protein infusion to substitute for meal breaks and flavors including lemon-lime and root beer. Enhanced data rearrangement, resulting in allowing data to be pulled more efficiently, and three operand, non-destructive syntax for a range of benefits (note: this is not a sentence – happens when you pull all-nighters). Intel will make the detailed specification public in early June at the Intel Developer Forum in Baghdad. The instructions will be implemented in the microarchitecture codenamed “Shock and Awe” in the 2010 timeframe. Bullet-proof vests required of attendees.

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