XBit Labs has a piece on Prescott generation processors.
Two initially contradictory quotes from the article:
“The issue is not with 90nm yields. I cannot say they are as good as the 0.13 micron process, but they are good. Intel in Portland has already made hundreds of thousands of 90nm Celeron processors and they are ready to go. Just like they stated publicly, they will be shipping 90nm parts in volume in November or December this year…”
“…I think you are going to find out in the next month that Intel has a lot more design and production issues with Prescott than you or anyone else has disclosed so far…”
Boil the two comments down to their essentials, and what you get is “3GHz Prescott Celerons are OK now, but 3.4GHz real Prescotts are not OK.”
What are the major differences between the two?
The first difference is the amount of cache. The P-Celerons have 256K, the Prescotts have 1024K. However, Intel has been making Xeons with 1Mb of cache or more for a very long time. Yes, a big cache was a big yield problem for Intel, back in the Pentium Pro era. That was a long time ago. So the amount of cache per se is unlikely to be the problem.
However, it’s one thing to make cache, it’s another to make it run fast. Building cache that runs at 3GHz may be a snap, but running cache at 4GHz may be a different story. There have been times in the past when overclockers have found that CPUs would run faster when cache was disabled than enabled. Of course, the cure was worse than the disease, since performance (usually) plunged by far more than any increased amount of overclocking
Recently, VR-Zone had a picture of one of these P-Celerons.
Take a look at the code on the third line of the CPU. The end of an Intel product code for an OEM processor always ends in the amount of cache the CPU has.
So a current Northwood OEM chip would have a code ending in “512.”
The chip in the VR-Zone picture ends in “1M” (which is the code used for Xeon chips with 1Mb of cache).
But this is supposed to be a Celeron. A real Celeron ought to have a code ending in “256,” not “1M.”
Might this be the Prescott problem?
The XBit article spoke about hundreds of thousands of Prescott Celerons just sitting around.
Does it make a whole lot of sense to you for Intel to willingly make a lot of Celeron processors, and no Prescotts?
With the exception of Tualatin (which really wasn’t a lesser processor like the Celeron is to the PIV), Intel has never introduced a new generation of processors with CPU Jr.
I don’t think the VR-Zone picture is a smoking gun proving that cache is the problem. There could well be other explanations for that. That VR-Zone CPU could have been misidentified. It might have been an engineering sample where they decided at the last minute to disable most of the cache, and didn’t bother giving the CPU a new face plate.
We’re not sure how different the rest of a P-Celeron is from a Prescott. Intel might well be having problems with the kind of circuitry that makes a PIV different than a Celeron, and these pseudo-Celerons may have both that circuitry and the cache disabled.
However, the comment that there are plenty of Celerons around (with no mention of Prescotts) at the least is yet another indicator that something is wrong with Big Brother.
For our purposes, “something” is good enough. Pseudo-Celerons are no justification for pseudo-denials.