Nehalem: Synchonized Voltages?

Synchronized voltages?  We think not.


The last few weeks, there’s been some rumors going around that overclocking on Nehalems will be severely limited because the voltages of the CPU and the memory are somehow “synchronized.”

When this rumor first came out, it struck me as being so not so that it wasn’t worthy of comment.  But since this concept has spread, it’s time to address this and try to figure out what is really going on.

Why is the concept so not so?

First, just to make sure we’re all on the same page, it seems that “synchronized voltages” is being interpreted to mean, “you have to run the CPU at the same voltage as the DDR3.”

This is so not so because the default voltages of Nehalem and DDR3 are so different.  The current (more on this later) DDR3 voltage is 1.5V.  In contrast, take a look at the CPU-Z voltage reported by these fine folks:

Intel Nehalem CPU-z

Yes, this is an ES and all that, but every recent Nehalem benchmarking shows a default voltage of less than 1V.   No matter what you assume in an attempt to get that number up, no way you get 1.5V as a default voltage number, so there’s no way CPU and memory voltages are “synchronized” at default.  

Is it possible that Nehalem has some core logic built-in that would do the following?


Yes, it is possible, in just about the same way it is possible I could go downstairs and guzzle down a quart of drain cleaner after finishing this article.   Such logic would be a suicide switch.  It’s certainly quite dramatic, and Hollywood would love the idea, but Hollywood doesn’t have a warranty department. 

Something like this might not even be a bad idea in the real world as an absolutely last-ditch measure to stop terrorists from overclocking, say, a nuclear reactor, and I’m sure Hollywood would like that idea, too.  But Intel folks have never struck me as being the Bruce Willis types, especially when they could just as easily do this,


stop folks just as dead in their tracks (less a CPU corpse), and make their warranty department a lot happier. 

This is not to say that this story of synchronization is completely fabricated.  What is a good deal more likely is that the story got garbled, more likely than not by the source of the story. 

It’s quite possible that in the Intel reference model, DDR3 voltage might be capped at 1.65V.  It’s quite possible that Nehalem could have a maximum voltage state of 1.65V, too.  It’s less likely, but possible, that the two somehow share a common voltage table.  In any event, the maximum voltage of the RAM is the relevant factor here, not the others.  In the past, voltage mods have taken care of that problem, and I suspect getting the voltage at least a bit higher is not beyond the skills of Taiwanese mobo designers.

The voltage issue gets trickier if the integrated memory controller controls the memory voltage.  A DIY memory voltage mod becomes much harder if not impossible, and probably would make the task of that Taiwanese mobo designer a good deal more difficult. 

Another conceivable speed bump is the possibility that Nehalems may require certain set synchronizations with its RAM, you may not have a wealth of memory dividers to choose from.  There would seem to be two of them with the initial “regular” Bloomfields, 800 and 1066MHz.  A memory voltage cap would carry a little more bite if, for example, you had to run everything at a 1:1 ratio. 

Any and all of this isn’t going to stop anyone determined enough to overclock these processors, and perhaps speed bumps is the most anyone can expect to encounter for Bloomfields.  However, my gut tells me that we’re missing the boat here.  There’s an unspoken assumption guiding these concerns, that FSB overclocking of Intel processors will continue more or less as it has in the past.  I think that is an unwarranted assumption, and I think you need to look no further than AMD’s processors to see why. 

For practical purposes, you cannot seriously FSB overclock AMD’s processors.  Yes, you can do it a little, but by nothing compared to Intel’s motherboards.  This little fact has been somewhat obscured by the relative lack of GHz for these processors and the existence of “black” multiplier-unlocked CPUs, but really, can you believe the same people who can make mobos that run Intel processors happily at 500MHz can’t make a 300MHz one for AMD processors?  (Correction: I should have said “Phenoms” rather than “AMD processors.”  X2s don’t have the kind of problems with FSBs that Phenoms have.) No, the finger of blame should point to the integrated memory controller of the AMD processor.  After all, it sets the parameters on memory speed; it decides the appropriate synchronization ratios between CPU and RAM, not the other way around, and while the memory speeds aren’t set in concrete, go beyond a certain point and it stops working.  

Is it so far-fetched to think that the same thing will happen will happen once Intel starts using an IMC, if not necessarily for Bloomfields, then for the mainstream Nehalem models?  

More on this tomorrow.  Update: Let’s make that Sunday. 


About Ed Stroligo 95 Articles
Ed Stroligo was one of the founders of in 1998. He wrote hundreds of editorials analyzing the tech industry and computer hardware. After 10+ years of contributing, Ed retired from writing in 2009.

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