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What exactly are the Latency timings, and is "relaxing" them to lower them or to raise them. Any input would be greatly appreciated.
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Latency?
- Thread starter altec
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Relaxing memory timings is to make them higher. This makes the memory slower because it takes more cycles to complete an operation but allows you to get higher fsb.
OP
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Ok, thats what I Thought, but what is the latency stand for, like what is it doing? Is it the speed that the memory runs through its cycles?
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the slower your timings are then the memory bandwith will be higher
i have a question too
say i have a stick of cas3 ram and i run it at cas2 and im at stock speeds will there be an increase in performance or will it be unstable?
i have a question too
say i have a stick of cas3 ram and i run it at cas2 and im at stock speeds will there be an increase in performance or will it be unstable?
Frequency, clock, period of synchronous operations
CPU, memory, PCI bus, GPU, ... are driven by a clock which oscillates many cycles per second. Cycle per sec is also know as Hertz (Hz). E.g. the famous Tbred B 1700+ can be overclocked to around 2,500,000,000 cycles/sec (or 2.5 GHz), DDR400 memory can operate at a clock frequency of 200,000,000 cycles/sec (or 200 MHz). The electronic components that are driven by a clock perform certain operatioins (electrically and logically) at each clock tick, and move on to the next one, .... This is also called the synchronous mode of operation.
The reciprocal of frequency f is called the period T of the clock. T=1/f. So the period T is the time spacing between two operations of the electronic componet, e.g CPU, memory, GPU, ... E.g for a 2.5 GHz CPU, the time spacing between each clock tick is 1/2.5GHz = 0.4 ns or 400 ps. The time spacing between each clock tick in a DDR400 memory module is 1/200MHz = 5 ns.
Latency
Latency is a measure of time to complete certain operations. For synchronous mode such as CPU, memory, ..., each operation is measured in terms of number of cycles. An operation can be a large operation such as the Read or Write operation, or the smaller internal operation of a Read or Write operation.
For DRAM memory modules that are driven by a clock is called synchronous DRAM (SDRAM). With this in mind, the memory operations can be described in terms of number of cycles instead of time. When we move from DDR400 to DDR500, or a CPU from 2GHz to 3GHz, each operation takes propotionally shorter time due to faster silicon process, but the number of cycles to achieve an operation remain the same, and the interrelationship between operations in terms of cycles remains the same, unless there is a change in architechture and timing, ...
DRAM is organized in rows and columns of storage bits. The intersection of a row and a column is a bit of data. To access data, address is decoded into row and column addresses. First, the row corresponding to the decoded row address is accessed followed by sensing of all the bits in that row (and are stored in the sense amplifier during the Read operation), and then the corresponding columns are accessed and data output. In many case, multiple columns are accessed and output as a sequence of data that are located on the same row to save row access overhead, this is called the burst mode of operation commonly used for large block/page of data (this is where CAS latency comes in).
Here use Read operation to illustrate the concept. After memory controller issues Read command and address, a DRAM read operation is like this:
1. DRAM module decodes address into row address and column address
2. Activates word-line (row address) and detect and store all the row data by the sense amplifiers
3a. Activates column (column address) and outputs data
3b. In case of multiple column access (as discuss earlier), a sequence of column data is output.
4. Restore data back to the DRAM cells and precharge for next operation.
The tRCD latency - is the time or number of cycles to perform step 2. Typically, tRCD takes 2 or 3 cyles to complete.
The CAS latency - is the time or number of cycles to perform step 3a. In case of step 3b (in case multiple N column data are output), the total latency = N x CAS. Typically, CAS latency takes 2 to 3 cycles to complete.
The tRP latency - is the time or number of cycles to perform step 4. Typically, tRP takes 2 or 3 cycles to complete.
So the latency of a DRAM Read operation is tRCD + N x CAS + tRP, where typically N = 1 or 4 or 8 (or even more), depends on the number of column access per memory access. This is the total number of cycles for a Read operation.
Remember tRCD = 2 or 3, CAS = 2 (try to avoid setting to CAS 3), tRP = 2 or 3,
For 1 column access, the total latency of Read operation = tRCD + CAS + tRP
For 4 column access, the total latency of Read operation = tRCD + 4 CAS + tRP
For 8 column access, the total latency of Read operation = tRCD + 8 CAS + tRP
etc, etc.
Time for first data output from address decode = tRCD + CAS
Time for data output in multiple column access,
Time for second data output = tRCD + 2 x CAS
Time for third data output = tRCD + 3 x CAS
etc, etc.
Latency is different than memory bandwidth. Memory bandwidth is solely determined by the memory bus frequency and FSB frequency, and NOT latency. It is how fast the memory clock or FSB clock can run, regardless of whether the memory module has shorter or longer latency.
E.g. all DDR400 memory module can run at same memory speed 200MHz, regardles of their latency, to deliver a maximum bandwidth given by 2x8x200 = 3200 MB/s. x2 because of DDR meaning data are transferred at both the rising and falling edges of the clock. x8 because there are 8 bytes in the memory bus. But some low latency module can finish each of the above steps tRCD or CAS or tRP in smaller number of cycles, e.g. at 2-2-2. Most module can finish each of these steps in longer number of cycles, e.g. 3-3-2.
CAS latency is the most important since it is the time to output 1 bit (single column access) or many bit of data (multiple column access) (as described earlier). For all today's memory module, always set CAS to 2, and I find that almost all modules in the market now can be able to do that.
Set tRCD and tRP to 2 is possible. If not, set them to 3 is OK, not much penalty.
Sorry for the long post, since I try to explain to myself as clear and complete as possible. Hope this helps.
CPU, memory, PCI bus, GPU, ... are driven by a clock which oscillates many cycles per second. Cycle per sec is also know as Hertz (Hz). E.g. the famous Tbred B 1700+ can be overclocked to around 2,500,000,000 cycles/sec (or 2.5 GHz), DDR400 memory can operate at a clock frequency of 200,000,000 cycles/sec (or 200 MHz). The electronic components that are driven by a clock perform certain operatioins (electrically and logically) at each clock tick, and move on to the next one, .... This is also called the synchronous mode of operation.
The reciprocal of frequency f is called the period T of the clock. T=1/f. So the period T is the time spacing between two operations of the electronic componet, e.g CPU, memory, GPU, ... E.g for a 2.5 GHz CPU, the time spacing between each clock tick is 1/2.5GHz = 0.4 ns or 400 ps. The time spacing between each clock tick in a DDR400 memory module is 1/200MHz = 5 ns.
Latency
Latency is a measure of time to complete certain operations. For synchronous mode such as CPU, memory, ..., each operation is measured in terms of number of cycles. An operation can be a large operation such as the Read or Write operation, or the smaller internal operation of a Read or Write operation.
For DRAM memory modules that are driven by a clock is called synchronous DRAM (SDRAM). With this in mind, the memory operations can be described in terms of number of cycles instead of time. When we move from DDR400 to DDR500, or a CPU from 2GHz to 3GHz, each operation takes propotionally shorter time due to faster silicon process, but the number of cycles to achieve an operation remain the same, and the interrelationship between operations in terms of cycles remains the same, unless there is a change in architechture and timing, ...
DRAM is organized in rows and columns of storage bits. The intersection of a row and a column is a bit of data. To access data, address is decoded into row and column addresses. First, the row corresponding to the decoded row address is accessed followed by sensing of all the bits in that row (and are stored in the sense amplifier during the Read operation), and then the corresponding columns are accessed and data output. In many case, multiple columns are accessed and output as a sequence of data that are located on the same row to save row access overhead, this is called the burst mode of operation commonly used for large block/page of data (this is where CAS latency comes in).
Here use Read operation to illustrate the concept. After memory controller issues Read command and address, a DRAM read operation is like this:
1. DRAM module decodes address into row address and column address
2. Activates word-line (row address) and detect and store all the row data by the sense amplifiers
3a. Activates column (column address) and outputs data
3b. In case of multiple column access (as discuss earlier), a sequence of column data is output.
4. Restore data back to the DRAM cells and precharge for next operation.
The tRCD latency - is the time or number of cycles to perform step 2. Typically, tRCD takes 2 or 3 cyles to complete.
The CAS latency - is the time or number of cycles to perform step 3a. In case of step 3b (in case multiple N column data are output), the total latency = N x CAS. Typically, CAS latency takes 2 to 3 cycles to complete.
The tRP latency - is the time or number of cycles to perform step 4. Typically, tRP takes 2 or 3 cycles to complete.
So the latency of a DRAM Read operation is tRCD + N x CAS + tRP, where typically N = 1 or 4 or 8 (or even more), depends on the number of column access per memory access. This is the total number of cycles for a Read operation.
Remember tRCD = 2 or 3, CAS = 2 (try to avoid setting to CAS 3), tRP = 2 or 3,
For 1 column access, the total latency of Read operation = tRCD + CAS + tRP
For 4 column access, the total latency of Read operation = tRCD + 4 CAS + tRP
For 8 column access, the total latency of Read operation = tRCD + 8 CAS + tRP
etc, etc.
Time for first data output from address decode = tRCD + CAS
Time for data output in multiple column access,
Time for second data output = tRCD + 2 x CAS
Time for third data output = tRCD + 3 x CAS
etc, etc.
Latency is different than memory bandwidth. Memory bandwidth is solely determined by the memory bus frequency and FSB frequency, and NOT latency. It is how fast the memory clock or FSB clock can run, regardless of whether the memory module has shorter or longer latency.
E.g. all DDR400 memory module can run at same memory speed 200MHz, regardles of their latency, to deliver a maximum bandwidth given by 2x8x200 = 3200 MB/s. x2 because of DDR meaning data are transferred at both the rising and falling edges of the clock. x8 because there are 8 bytes in the memory bus. But some low latency module can finish each of the above steps tRCD or CAS or tRP in smaller number of cycles, e.g. at 2-2-2. Most module can finish each of these steps in longer number of cycles, e.g. 3-3-2.
CAS latency is the most important since it is the time to output 1 bit (single column access) or many bit of data (multiple column access) (as described earlier). For all today's memory module, always set CAS to 2, and I find that almost all modules in the market now can be able to do that.
Set tRCD and tRP to 2 is possible. If not, set them to 3 is OK, not much penalty.
Sorry for the long post, since I try to explain to myself as clear and complete as possible. Hope this helps.
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Analogy on Bus Speed, Bandwidth and Latency:
In a two lane highway, all vehicles in BOTH lanes are moving at 60 mph. All the vehicles on one lane (called CAS3) are all identical long vans. All the vehicles on the other lane (called CAS2) are all identical compact cars.
Since vehicles in both lanes are driving at SAME speed, the total vehicle-length passed at a given point per second in both lanes are the same. This is analogous to the memory bus speed or bandwidth being the SAME in two different memory buses each connected to a different module, one to CAS3 and one to CAS2. Clock pulses are moving in both buses at same rate, even one memory has higher latency CAS3 (takes more time to finish an operation) than the other CAS2.
But if you count the number of vehicles passing through each lane per second, the number on lane CAS3 is much smaller than that on lane CAS2. This is analogous to the number of data packets that can be delivered to the CPU per second on the bus by CAS3 memory is much less than that by CAS2 memory.
Data (clock pulses) are moving at the same speed in both cases (same memory frequency, same BW), but the data packets received by the CPU is much less in the case of larger latency memory (CAS3) than that of smaller latency memory (CAS2)
In a two lane highway, all vehicles in BOTH lanes are moving at 60 mph. All the vehicles on one lane (called CAS3) are all identical long vans. All the vehicles on the other lane (called CAS2) are all identical compact cars.
Since vehicles in both lanes are driving at SAME speed, the total vehicle-length passed at a given point per second in both lanes are the same. This is analogous to the memory bus speed or bandwidth being the SAME in two different memory buses each connected to a different module, one to CAS3 and one to CAS2. Clock pulses are moving in both buses at same rate, even one memory has higher latency CAS3 (takes more time to finish an operation) than the other CAS2.
But if you count the number of vehicles passing through each lane per second, the number on lane CAS3 is much smaller than that on lane CAS2. This is analogous to the number of data packets that can be delivered to the CPU per second on the bus by CAS3 memory is much less than that by CAS2 memory.
Data (clock pulses) are moving at the same speed in both cases (same memory frequency, same BW), but the data packets received by the CPU is much less in the case of larger latency memory (CAS3) than that of smaller latency memory (CAS2)
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OP
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Wow, thanks for that in-depth explanation. It all seems a little clearer to me now.
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Thanks hitechjb1, you answered a lot of questions this noobie has. I love this forum!!! 
So, what are RAS, RAS to CAS delay, RAS precharge, Tras (cycle time), Trc?
I'm just reading off the fields from CPU-Z that weren't covered yet...anyone want to chip in? This stuff still boggles me (acronyms aren't my forte anyway hehe)
Also...is CPU-Z very accurate at knowing what kind of memory you have? I supposedly have 2 sticks of Nanya, but CPU-Z is saying they're Micron (?!?!)
Also, my BIOS said CAS is 2.5, but cpu-z calls it's 3.0. weird.
I'm just reading off the fields from CPU-Z that weren't covered yet...anyone want to chip in? This stuff still boggles me (acronyms aren't my forte anyway hehe)
Also...is CPU-Z very accurate at knowing what kind of memory you have? I supposedly have 2 sticks of Nanya, but CPU-Z is saying they're Micron (?!?!)
Also, my BIOS said CAS is 2.5, but cpu-z calls it's 3.0. weird.
Penance said:
RAS to CAS delay is tRCD, the time to perform step 2 described in the prevous post. Typically it is 2 or 3. 2 is better.
RAS precharge, or RAS precharge delay is tRP, the time to preform step 3 described earlier. Typically it is 2 or 3. 2 is better.
tRAS, active to precharge delay, is the minimum time for an active access (to perform a single row and column access. So tRAS >= tRCD + CAS. It is the least important number on performance, set it to 5 or 6 is OK. (Be honest, I am sometime confused by how the bios is implementing it, and the definiton is not very clear. But luckily, it is not of big significant.) For example, typically, tRCD = 3, CAS =2 , so tRAS >= 5 (6 is OK, 5 should work). If tRCD = 2, CAS = 2, so tRAS >= 4 (5, 6 is OK).
Sometimes bios setting, and how the bios takes the number and operates become even harder to understand, since it is mb specific and also depends how the programs read those data and present them.
After going through all these terms, operation details, theory, ... just to use and set up memory is VERY SIMPLE. For current mb's and memory modules, 6-3-3-2 is almost certain would work, and it won't lose too much performance to more aggressive timing 5-2-2-2, 2-3% at most. Those number are in this order: tRAS-tRCD-tRP-CAS.
But setting FSB as high as possible, as permitted by mb and memory, even having to go from 5-2-2-2 to 6-3-3-2, would benefit the most for overall system bandwidth, 3D video and gaming performance. Set CAS to 2 is the most important among these magic numbers, and I find almost all module on the market today can do CAS2.
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Which memory to buy?
Since FSB and memory bus speed are much more important for system performance than those latency settings: tRAS, tRCD, CAS, tRP.
So if two modules PC3500 6-3-3-2 and PC3200 6-2-2-2, are about the same price, I would just buy the PC3500 6-3-3-2 module instead of the other.
Reason:
1. The module marked PC3500 officially claims to perform at 217 MHz (if not RMA or money back). 6-3-3-2 won't lose much to 6-2-2-2. Also it may even work at better latency setting (don't count on this).
2. The module marked PC3200 officially claims to work only up to 200 MHz. If it turns out to fail at 201 MHz (it is possible, it is NOT always overclockable), you cannot complain and RMA. You would then lose 16 MHz of memory bandwidth = 256 MB/s !!!
Since FSB and memory bus speed are much more important for system performance than those latency settings: tRAS, tRCD, CAS, tRP.
So if two modules PC3500 6-3-3-2 and PC3200 6-2-2-2, are about the same price, I would just buy the PC3500 6-3-3-2 module instead of the other.
Reason:
1. The module marked PC3500 officially claims to perform at 217 MHz (if not RMA or money back). 6-3-3-2 won't lose much to 6-2-2-2. Also it may even work at better latency setting (don't count on this).
2. The module marked PC3200 officially claims to work only up to 200 MHz. If it turns out to fail at 201 MHz (it is possible, it is NOT always overclockable), you cannot complain and RMA. You would then lose 16 MHz of memory bandwidth = 256 MB/s !!!
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OP
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hitechjb1, I have some HyperX pc3500, and for some reason my FSB wont stabily go past 203. My timings are: 7-2-2-2, I have tried lowering the multiplier on my CPU to see if it's that that is holding me back, and my FSB still wont go higher. My vdimm is set to 2.8v, and my chipset voltage is set to 1.7. I can't figure out where the bottleneck is. It obviously isn't the ram since it is rated to run at 217 FSB, and it isn't my CPU since I have ruled that out by lower the multiplier so that my overall oc is at 2.2Ghz (stable with 203 FSB at 2.45Ghz), and I don't think that my board is causing any problems since the majority of people can take the NF7-S Revision 2 to 220FSB and higher with pc3000 or pc3200. Any suggestions?
altec said:
Have you tried these:
1. As I recall (haven't check lately for sure) Hyper X 3500 has ras/cas timing spec'ed to 7-3-3-2. Definitely, it is not spec'ed at 7-2-2-2. Maybe it does not like 7-2-2-2, have you tried setting it to 6-3-3-2 or 7-3-3-2.
2. Do you have cooling on the south bridge. FSB overclocking problem has a lot to do with NB, SB cooling and chipset Vdd. Does the mb allow chipset Vdd adjustment in the bios, have you adjusted them if so?
3. MB can vary, it is spec at 200 MHz FSB, but sometime things can be good or bad. If really unlucky, it may get max out at around 200 MHz. E.g. for the first batch of nforce2, some ppl can go only to 180 MHz FSB, some can go to 210 MHz at stock, without Vdd mod.
4. Even the memory is spec at 217 MHz, sometimes memory can be bad even brand new brand names. Have you tried the Hyper X on another mb that has been able to run at 220 MHz, so you know for sure the modules are good at 217 MHz at certain timing and Vdimm.
Try these and let us know.
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OP
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I have tried 7-3-3-2 with no positive results. The reason that it is at 7-2-2-2 right now is because that is what the board states as "Optimal timings" so I tried it there.
I dont have cooling on the SB, so that could be one of my problems, and I will look into it. I have adjusted the chipset voltage to 1.7, which is the highest settin that it will go (stock was 1.6 i think).
I dont have another good board to test the memory in. My only other board is a Soyo KT400, and when I tried to run this memory in that board the FSB wouldn't go past 170.
I dont have cooling on the SB, so that could be one of my problems, and I will look into it. I have adjusted the chipset voltage to 1.7, which is the highest settin that it will go (stock was 1.6 i think).
I dont have another good board to test the memory in. My only other board is a Soyo KT400, and when I tried to run this memory in that board the FSB wouldn't go past 170.
altec said:
Try to find some way to test the HyperX, so you can elminate one unknown or uncertainty.
When one buys expensive parts like memory, make sure there is some way to test the memory within the money back allowed time. Since nothing is guaranteed until it is tested by oneself for sure.
Even brand name, brand new, expensive memory can come with a bad stick or under specification. I once bought a brand new Corsair 3500C2, and it was a bad stick, thousand of errors at stock frequency and under spec by 20 MHz.
Altec, you can try this also.
How to test memory at frequency much higher than what FSB allows
One way you can test your HyperX or any memory stick at frequency much higher than what the FSB allows is as follows:
You can test the memory by using ASYNC mode of your mb (most mb can do this), and set the memory speed to fsb such than memory speed is HIGHER than the FSB at a ratio. And the FSB is running much slower than the speed that it normally can, and hence would not be a limiting factor. You can use memtest86 looping to test the memory at the spec frequency, timing and voltage. If it passes, you can even boot into windows and run prime95, 3DMark, ... to see whether the memory can run at the speed in question under real system conditions, ...
E.g. set FSB to 150 MHz, memory to fsb ratio = 4:3, so memory frequency is 150 x (4/3) = 200 MHz. That means you can test memory at 200 MHz by running FSB at 150 MHz. It should work fine like this.
Then for example, set FSB to 160 MHz, memory would then be 160 x (4/3) = 213 MHz (much closer to the 217 MHz rated frequency of the PC3500) and run the test.
If it passes, then increase the FSB by small steps of MHz when it is getting close to the rated frequency or the max oc frequency of the memory. Keep increasing FSB slowing until the memory begins to fail and/or system becomes unstable. This would give you the max memory frequency at certain memory timing and voltage.
After the test to find out the max frequency of the memory, set the bios back to SYNC as usual.
How to test memory at frequency much higher than what FSB allows
One way you can test your HyperX or any memory stick at frequency much higher than what the FSB allows is as follows:
You can test the memory by using ASYNC mode of your mb (most mb can do this), and set the memory speed to fsb such than memory speed is HIGHER than the FSB at a ratio. And the FSB is running much slower than the speed that it normally can, and hence would not be a limiting factor. You can use memtest86 looping to test the memory at the spec frequency, timing and voltage. If it passes, you can even boot into windows and run prime95, 3DMark, ... to see whether the memory can run at the speed in question under real system conditions, ...
E.g. set FSB to 150 MHz, memory to fsb ratio = 4:3, so memory frequency is 150 x (4/3) = 200 MHz. That means you can test memory at 200 MHz by running FSB at 150 MHz. It should work fine like this.
Then for example, set FSB to 160 MHz, memory would then be 160 x (4/3) = 213 MHz (much closer to the 217 MHz rated frequency of the PC3500) and run the test.
If it passes, then increase the FSB by small steps of MHz when it is getting close to the rated frequency or the max oc frequency of the memory. Keep increasing FSB slowing until the memory begins to fail and/or system becomes unstable. This would give you the max memory frequency at certain memory timing and voltage.
After the test to find out the max frequency of the memory, set the bios back to SYNC as usual.
OP
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DO you have any idea on how to set the board to async...I spent like 20min looking for it last night before I gave up.
OP
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I also changed the timings to 7-3-3-2, and can boot and run Prime all night with 207FSB, but anything higher will give me errors. This is a little improvement, but I am looking for at least the 217 FSB that this stuff ir rated to run at. Any other suggestions??
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