The thing many people forget to realize is that as the clock cycle of chips is reduced, the timings will have to go up no matter what. You prolly won't see 2-2-2-6 timings on a 4ns chip, and if you do it won't be for some time. 10ns seems to be the limit for CAS Latency, CAS-to-RAS Delay, and RAS-precharge. 4ns chips running at DDR500 with timings of 3-3-3-8 will reach 12ns, with a CL of 2.5 they reach a CL of 10ns.