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Arrow Lake leaks

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mackerel

Member
Joined
Mar 7, 2008

The original tweet that had the slides has been taken down, but this is a glimpse of Intel's next desktop gen. There may be three dies: 8P+16E, 6P+16E, 6P+8E. Assuming the same exchange rate, that puts them roughly in 12, 10 and 8 core area terms.

It is noted it may not include HT, so those counting threads may find it lacking. I personally find threads over-valued as on average they give comparably little, with the odd outlier seeing a meaningful speedup like Cinebench at ~30%. Not having HT does save a little die area, and reduces some scheduling complexity which may lead to more consistent performance, and closing the door on potential cross-thread vulnerabilities.

Not mentioned is Intel has said this is targeted on their 20A process, which is a massive jump from 7. I'm out of date on what core will be used when but it is expected to use a newer microarchitecture than Meteor Lake, or two on from Raptor Lake.

While Intel have managed to generally keep up with AMD in performance but not at power efficiency, this might be the generation where they catch up in that area too. Will be one to watch.
 

The original tweet that had the slides has been taken down, but this is a glimpse of Intel's next desktop gen. There may be three dies: 8P+16E, 6P+16E, 6P+8E. Assuming the same exchange rate, that puts them roughly in 12, 10 and 8 core area terms.

It is noted it may not include HT, so those counting threads may find it lacking. I personally find threads over-valued as on average they give comparably little, with the odd outlier seeing a meaningful speedup like Cinebench at ~30%. Not having HT does save a little die area, and reduces some scheduling complexity which may lead to more consistent performance, and closing the door on potential cross-thread vulnerabilities.

Not mentioned is Intel has said this is targeted on their 20A process, which is a massive jump from 7. I'm out of date on what core will be used when but it is expected to use a newer microarchitecture than Meteor Lake, or two on from Raptor Lake.

While Intel have managed to generally keep up with AMD in performance but not at power efficiency, this might be the generation where they catch up in that area too. Will be one to watch.
So, are these CPUS not good for gaming????From what I read it seems like it is for workstation's and servers I might have read it wrong.:shrug:
 
What makes you think that? It's newer cores than existing. I know, it doesn't necessarily mean it is better, for example if other design priorities were picked over performance. But in general it is a balance of progressing both performance and efficiency and we have a major jump in process node to go along with it.
 
Arrowlake should be a solid product but probably will not catch the competition. For consumer use (more specifically DIY), I hope they fix their cache/memory latency issue that is present on MTL. Going from a monolithic design to chiplet/tiles really hurt their cache/mem latencies, which will be bad for gaming. They can get away with it on mobile because MTL's iGPU isn't good enough to expose the weakness in the CPU and the majority of dGPU laptops go with RPL refresh, but on desktop, it could get ugly. Hopefully they have a solution for ARL ready.

The lack of HT on ARL won't be a big deal at the top end of the product stack, but there might be some lower end SKUs that feel some pain (in regards to competitive standing) from it.
 
20A/2nm is all marketing at this point and has almost no real world definition. Its at best a general average of the transistor size.
 
20A/2nm is all marketing at this point and has almost no real world definition. Its at best a general average of the transistor size.

The big change is that this is Intel's first GAA (gate all around) process which is the next step after FinFETs. TSMC's GAA process comes towards the end of 2025. Samsung already has one but its yields suck and I'm not even sure the performance is all that great for logic designs.

The other thing Intel is introducing first before anyone is BS-PDN (backside power distribution network) which places the signal lines and power lines on opposite sides of the devices (rather than on the same side as done currently). This will allow for slightly improved frequencies or more efficient designs, but increases costs and introduces thermal issues (Intel says they have a solution for the thermal issues though). The big question mark will be yield and capacity. Just like 4 nm will be very short lived, 20a will be very short lived (and low capacity) in favor of introducing 18a, where they plan to offer the process for outside customers.

Edit: to add to the naming conventions, it's really become about how tightly you can space the transistors together and the electrical performance of the transistors, rather than the size of the transistor itself, which isn't really getting any smaller to scale with the node labels.
 
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It's on Intel's 20A process 2nm now how much smaller then 2nm will it get?

Intel has 18a and 14a coming in the next few years. Probably 10a comes after that and there is research going on down to 1a. With that said, these are just node labels at this point and don’t actually mean anything in terms of feature size.
 
Intel has 18a and 14a coming in the next few years. Probably 10a comes after that and there is research going on down to 1a. With that said, these are just node labels at this point and don’t actually mean anything in terms of feature size.
Ok now I understand.:)
 
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