Basic Memory Questions

[dw85745]

I just got CPU-Z and used it on on my old system.

The SDRAM memoy is labeled at 100 / 133 MHz.
However the JEDEC tables inside CPU_Z show:

CHIP.....................JEDEC..........JEDEC.........JEDEC
1.............................................100...........133
2.............................................................142
3...........................................133.............142

The processor is as follows:
Core Speed 1100.2 MHz
Multiplier x Bus Speed 11.0 x 100.0 MHz
Rated Bus speed 200.0 MHz (I assume this is NOT actual as jumpers set to auto)


The memory runs fine with the BIOS Memory set to 100 MHz.
However, the system becomes unstable with BIOS memory set to 133Mhz.

My assumption is the 142 memory adjusts down to 133 since it is rated higher.
Or am I wrong?


QUESTION:
Can someone please explain why the system is unstable with the memory set at 133Mhz?
My ASSUMPTION is some relationship between CPU, FSB running at 100Mhz?

(BTW not trying to overclock yet -- newbee, just trying to understand).

Thanks David

 

[rayraysfunhouse]

Post pictures of cpu-z cpu tab , memory tab, and speed tab so we have a better picture of what you are talking about so we can help better.

 

[dw85745]

OK:

CPU-Z TXT Report
-------------------------------------------------------------------------

Binaries
-------------------------------------------------------------------------

CPU-Z version 1.71.0.x32

Processors
-------------------------------------------------------------------------

Number of processors 1
Number of threads 1

APICs
-------------------------------------------------------------------------

Processor 0
-- Core 0
-- Thread 0 0

Timers
-------------------------------------------------------------------------

ACPI timer 3.580 MHz
Perf timer 3.580 MHz
Sys timer 1.000 KHz


Processors Information
-------------------------------------------------------------------------

Processor 1 ID = 0
Number of cores 1 (max 1)
Number of threads 1 (max 1)
Name AMD Athlon XP
Codename Palomino
Specification AMD Athlon(tm)
Package Socket A (462)
CPUID 6.6.2
Extended CPUID 7.6
Core Stepping A5
Technology 0.18 um
Core Speed 1100.2 MHz
Multiplier x Bus Speed 11.0 x 100.0 MHz
Rated Bus speed 200.0 MHz
Instructions sets MMX (+), 3DNow! (+), SSE
L1 Data cache 64 KBytes, 2-way set associative, 64-byte line size
L1 Instruction cache 64 KBytes, 2-way set associative, 64-byte line size
L2 cache 256 KBytes, 16-way set associative, 64-byte line size
FID/VID Control no

K7 Thermal sensor yes


Thread dumps
-------------------------------------------------------------------------

CPU Thread 0
APIC ID 0
Topology Processor ID 0, Core ID 0, Thread ID 0
Type 02001002h
Max CPUID level 00000001h
Max CPUID ext. level 80000008h
Cache descriptor Level 1, I, 64 KB, 1 thread(s)
Cache descriptor Level 1, D, 64 KB, 1 thread(s)
Cache descriptor Level 2, U, 256 KB, 1 thread(s)

CPUID
0x00000000 0x00000001 0x68747541 0x444D4163 0x69746E65
0x00000001 0x00000662 0x00000000 0x00000000 0x0383F9FF
0x80000000 0x80000008 0x68747541 0x444D4163 0x69746E65
0x80000001 0x00000762 0x00000000 0x00000000 0xC1C3F9FF
0x80000002 0x20444D41 0x6C687441 0x74286E6F 0x0020296D
0x80000003 0x00000000 0x00000000 0x00000000 0x00000000
0x80000004 0x00000000 0x00000000 0x00000000 0x00000000
0x80000005 0x0408FF08 0xFF20FF10 0x40020140 0x40020140
0x80000006 0x00000000 0x41004100 0x01008140 0x00000000
0x80000007 0x00000000 0x00000000 0x00000000 0x00000001
0x80000008 0x00002022 0x00000000 0x00000000 0x00000000

MSR 0xC0010114 0x8668CF68 0xFFFFFFFF
MSR 0xC0010015 0x00000000 0x00001008



Chipset
-------------------------------------------------------------------------

Northbridge VIA KT133A rev. 03
Southbridge VIA VT82C686 rev. 40
Graphic Interface AGP
AGP Revision 3.0
AGP Transfer Rate 4x
AGP SBA supported, enabled
Memory Type SDRAM
Memory Size 1536 MBytes
Memory Frequency 133.4 MHz (FSB + 33 MHz)
DRAM Interleave none
CAS# latency (CL) 3.0
RAS# to CAS# delay (tRCD) 3
RAS# Precharge (tRP) 3
Cycle Time (tRAS) 6

Memory SPD
-------------------------------------------------------------------------

DIMM # 1
SMBus address 0x50
Memory type SDRAM
Manufacturer (ID) (00000000000000000000)
Size 512 MBytes
Max bandwidth PC142 (142 MHz)
Part number
Number of banks 2
Data width 64 bits
Correction None
Registered no
Buffered no
EPP no
XMP no
AMP no
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 3.0-3-3-7-n.a. @ 142 MHz

DIMM # 2
SMBus address 0x51
Memory type SDRAM
Manufacturer (ID) Kingston (7F980000000000000000)
Size 512 MBytes
Max bandwidth PC133 (133 MHz)
Part number 64MX64PC133CL3168
Serial number 061242E0
Manufacturing date Week 32/Year 04
Number of banks 2
Data width 64 bits
Correction None
Registered no
Buffered no
EPP no
XMP no
AMP no
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 2.0-2-2-5-n.a. @ 100 MHz
JEDEC #2 3.0-3-3-6-n.a. @ 133 MHz

DIMM # 3
SMBus address 0x52
Memory type SDRAM
Manufacturer (ID) Micron Technology (2CFFFFFFFFFFFFFF0000)
Size 512 MBytes
Max bandwidth PC142 (142 MHz)
Part number 16LSDT6464AG-13ED2
Serial number 072CE131
Manufacturing date Week 11/Year 05
Number of banks 2
Data width 64 bits
Correction None
Registered no
Buffered no
EPP no
XMP no
AMP no
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 2.0-2-2-6-n.a. @ 133 MHz
JEDEC #2 3.0-3-3-7-n.a. @ 142 MHz

DIMM # 1
SPD registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
00 80 08 04 0D 0A 02 40 00 01 70 52 00 80 08 00 01
10 8F 04 04 01 01 00 0E A0 80 00 00 14 0F 14 2D 40
20 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00
30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 E8
40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 F5
80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
90 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

DIMM # 2
SPD registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
00 80 08 04 0D 0A 02 40 00 01 75 54 00 82 08 00 01
10 8F 04 06 01 01 00 0E A0 60 00 00 14 0F 14 2D 40
20 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00
30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 D3
40 7F 98 00 00 00 00 00 00 04 20 36 34 4D 58 36 34
50 50 43 31 33 33 43 4C 33 31 36 38 50 20 04 20 06
60 12 42 E0 FF FF FF FF FF FF FF FF FF FF FF FF FF
70 FF FF FF FF FF FF FF FF FF FF FF FF FF FF 64 F7
80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
90 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
F0 39 39 30 35 32 32 30 2D 30 30 37 2E 41 30 30 00

DIMM # 3
SPD registers
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
00 80 08 04 0D 0A 02 40 00 01 70 54 00 82 08 00 01
10 8F 04 06 01 01 00 0E 75 54 00 00 0F 0E 0F 2D 40
20 15 08 15 08 00 00 00 00 00 3C 00 00 00 00 00 00
30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 B8
40 2C FF FF FF FF FF FF FF 01 31 36 4C 53 44 54 36
50 34 36 34 41 47 2D 31 33 45 44 32 02 00 05 0B 07
60 2C E1 31 00 00 00 00 00 00 00 00 00 00 00 00 00
70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 FF
80 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
90 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 0F


Monitoring
-------------------------------------------------------------------------

Mainboard Model 8363-686A (0x000001E6 - 0x02348A74) << This is a Soyo SY-K7VTA-Pro

 

[rayraysfunhouse]

Oh wow that's one way. Guess I should have said make screenshots and upload the pictures. My apologies.

 

[dw85745]

No apologies necessary. Appreciate you responding to my thread.

 

[rayraysfunhouse]

That's what were here for.

 

[dw85745]

Just saw you are at Fort Sill. My nieces husband is stationed there.

 

[rayraysfunhouse]

Lol yea I've been here for 6 years off and on.

 

[dw85745]

He's cycled through a couple times himself.

BTW, do you want screen shots instead of the text I posted?
If so, will have to wait to this evening as CPU-Z crashed my system with the programs I have running.
Restarted them and will be done by around 8:00 PM your time before I can get pics.

 

[rayraysfunhouse]

Yes screen shots are easier to read than the text.

 

[dw85745]

OK. Screen shots it is.

 

[dw85745]

Program finished early so 5 pics.
Again thanks for your time on my behalf.

David

 

[Mr.Scott]

I'll try to keep it understandable.
You motherboard has no PCI lock. Therefore when you try to increase the bus speed to 133, it also increases all the other buses with it. Most peripheral devices like hard drives can't stand that much bus increase and will either lock up or BSOD your machine. Max you'll get bus wise is around 120. You'll never reach that 142 ram speed figure on that board unless it has positive ram dividers, which I doubt it does.
Newer boards all pretty much have a way to lock the PCI bus now. Back when your board was current, only one chipset manufacturer had PCI locks. That would have been the NF2 chipset by Nvidia. All the rest, like your Via chipset had no locks.

You would have to use a CPU that has a native bus speed of 133 to achieve what you want. The one you're currently using is natively 100.

 

[dw85745]

Mr. Scott: Thanks for the clear and concise explanation.
I see I still have some homework to do.
Thought I had a "relatively" good understanding of the relationship between the CPU, FSB, and Memory,
but:

1) PCI locks is a something new -- for me -- in the equation, as well as
2) Peripheral devices being affected. (makes sense since they need the bus for their signals).


============= QUESTION =================

One other question.

WHen I had 3 sticks of 256 on the board, I ran memory at 133 MHz and never had an issue.
Only when I increased it to capacity (3 stick of 512), did the problem arise and the
need to lower memory bus speed to 100 MHz.

So why with lower memory did I NOT have an issue?

===============================================

Have a nice day, and thank you again for your time on my behalf.

David

=============== FOLLOWUP - FWIW ====================

Pulled the docs for the board.

The BIOS has an Auto Detect DIMM/PCI Clk which I disabled when I first started adjusting the DRAM Clock to PC133 with the 3 x 512 sticks.
The MYOB jumpers were still configured to CPU auto and the dip switches (which apply to the jumper being set to manual was still set at an 11 multiple)
So my guess is the jumpers would override the BIOS and the CPU would still be in control.

The jumpers for the FSB are set for 200MHz ( have two FSB options -- 200 Mhz and 266 Mhz).
There is no BIOS for the FSB so with CPU auto my guess iis the FSB is running the same as the CPU.

So maybe toggling the DIMM/PCI Clk to Disabled, left the CPU running at its rated speed (Assume 100 Mhz ) but caused the FSB to bump to 200MHz because the
FSB jumpers were now in play ??

 

[Mr.Scott]

The BIOS has an Auto Detect DIMM/PCI Clk which I disabled when I first started adjusting the DRAM Clock to PC133 with the 3 x 512 sticks.

Again, it has to do with the age of the board. Back then, maximum memory for socket A was pretty much 1 gig, with 512 being the better performer. The socket A memory controller was never meant to handle over a gig of ram. You might want to try just 2 of your 512 sticks and see if that makes a difference.

The jumpers for the FSB are set for 200MHz ( have two FSB options -- 200 Mhz and 266 Mhz).
There is no BIOS for the FSB so with CPU auto my guess iis the FSB is running the same as the CPU.

So maybe toggling the DIMM/PCI Clk to Disabled, left the CPU running at its rated speed (Assume 100 Mhz ) but caused the FSB to bump to 200MHz because the
FSB jumpers were now in play

Your CPU runs at 100MHz base clock (FSB). This is the same thing as your ram running at 200MHz. Reason being is the ram runs at a double pumped clock cycle.

If you set the jumpers to 133MHz, you would essentially be overclocking the CPU, which you might get away with, and that would bring your ram up to 133MHz also, but that will also depend on how much ram you run.
Realistically, the memory controller was made for a gig of ram or less and this is where I think your problem lies.

 

[dw85745]

Mr. Scott:

Thank you again for your post.
I hear you.

FWIW:
The Soyo board docs say it will support up to 1.5GB of RAM. It also says the DRAM interface may be +/- 33 Mhz than the CPU to allow the use of PC66 or PC 133 modules.

=========================
One area I was just doing some reading on -- but can't find exactly what I'm after is:
How each controller affects (or compensates) for the differences in other timings.

For example: If the CPU is running at 100 Mhz (or some multiple of) and you have a DRAM chip rated at 100 MHz then they "are in sink timing wise" since the DRAM is running at the
same MHz (or some multiple of) the CPU Mhz. With PC133 they are Not in sink (not cyclically) from a MHz perspective.
So when the SDRAM pushes the data onto the Northbridge or L2 cache where it is buffered and a flag is set to tell the CPU "I have data"
then the CPU timing should be responsible for picking up this data from the buffer (Northbridge or L2) and handling it.
So the timing between the RAM and the Northbridge or L2 should have no bearing on the speed at which the CPU is running since they are independent of each other.
So why would changing the SDRAM timing impact the CPU?

NOTE: I recognize this is different than the chipset not being able to handle more than 1Gig of RAM.

David