Is this why Ryzen is having problems with higher RAM frequencies?

[gupsterg]

Yeah RAM is nutty prices at present. I was able to luckily grab some Trident Z F4-3200C14D-16GTZ prior to Ryzen launch on a crazy promo of ~£77, now your looking at ~double+ for same kit.

A new addition to AGESA 1.0.0.6 is CLDO_VDDP. This voltage wasn't in / differs from VDDP on previous UEFI. In current UEFI you can just ignore VDDP.

CLDO_VDDP programs the on die regulators. Tweaking this voltage resolves memory training hole. It does not "plug" it as such, it moves the hole to another range of memory frequency. Increasing/decreasing the frequency changes direction of hole up or down the MHz range. Which direction the hole moves is difficult to determine due to how this voltage is, link to The Stilt's post, granularity information.

For example a R7 1700 CPU sample worked like this with it on [Auto] (preset 950mV on C6H).

I pick memory frequency : 2800MHz > trains > 2933MHz > trains > 3066MHz > trains > 3200MHz > trains > 3333MHz > fails

So next I adjust CLDO_VDDP on a working RAM frequency, say 2800MHz and set CLDO_VDDP to 937mV, now I repeat testing.

I pick memory frequency : 2800MHz > trains > 2933MHz > trains > 3066MHz > trains > 3200MHz > fails

Now I know the memory hole has moved as a working frequency has stopped working. Due to how the AMD CBS section will reset on a memory training fail (Q-Code: F9) I go back to 2800MHz and re-setup CLDO_VDDP as 937mV. Now I train RAM without going to 3200MHz.

I pick memory frequency : 2800MHz > trains > 2933MHz > trains > 3066MHz > trains > 3333MHz > trains

(Note: Caveat for above is RAM timings, VDIMM, SOC, etc have been set correctly so a memory training error does not occur due to them)

From my own testing/members shares it is best to setup some of the RAM options prior to "jumping" RAM frequencies. For example there is a setting in AMD CBS that The Stilt advised users of 1DPC SR should disable, BankGroupSwap. A CLDO_VDDP voltage that works to resolve a RAM MHz hole with it as [Auto/Enabled] did not work for me when [Disabled].

Changing RAM timings after successfully resolving a memory hole using CLDO_VDDP has not been an issue for my CPU samples.

Another pearl of wisdom from The Stilt is regarding what we would term as RAM straps

The newer FWs used in these bioses are still betas (as are the bioses themselves), so few shenanigans are no surprise really. The newer FWs are also completely different animals to the ones used in earlier AGESA versions, so don't expect them to behave even remotely the same.

Also, there are no "straps" in these CPUs. There are several timings which AGESA tries to keep constant, independent of the MEMCLK. These timings only change to reflect the change required in the resulting cycle time. For example if a certain timing defaults to 8 CLKs at 2133MHz MEMCLK (7.5ns cycle time), at 3200MHz MEMCLK the same timing must be configured to 12 CLKs for the cycle time to remain the same (7.5ns).