Hello,
I have a quad socket machine running x4 6274's as shown below
https://kudlaengineering.wordpress.com/2013/02/24/64-core-kopernik-is-born/
I am running CFD simulations on unstructured grids, so I require great bandwidth between my cpu's and ram (as I understand it, if populated correctly you will get quad channel).
I currently have x4 DDR-1600 ECC in P1-1A, P1-2A, P1-3A, P1-4A (all are next to CPU1). My questions:
1) Am I taking advantage of quad channel communication for all procs?
2) If I leave it like this, what is the performance penalty (just order of magnitude, or is it just couple%)?
Thanks for your help -
Tom
I have a quad socket machine running x4 6274's as shown below
https://kudlaengineering.wordpress.com/2013/02/24/64-core-kopernik-is-born/
I am running CFD simulations on unstructured grids, so I require great bandwidth between my cpu's and ram (as I understand it, if populated correctly you will get quad channel).
I currently have x4 DDR-1600 ECC in P1-1A, P1-2A, P1-3A, P1-4A (all are next to CPU1). My questions:
1) Am I taking advantage of quad channel communication for all procs?
2) If I leave it like this, what is the performance penalty (just order of magnitude, or is it just couple%)?
Thanks for your help -
Tom