(btw I think the reason why you need to connect ak4 is because if you don't the cpu will not read / or will read at the improper time (before the signals have stabilized) the configuration of some configuration pins during reset - this isn't mentioned in the datasheet, but that's my theory. It could be wrong of course, just a speculation.)
Super idea to try that!
I think the original thought was that a Tualatin would not boot at all if there's no connection to vtt_powergood, so the mod "pioneers" took something seemingly close in function and connected to that.
Turns out it does boot without AK4 connection though, but often at the penalty of being unstable -- so I'm not sure there's a problem reading the config pins. I'd figure it would not boot at all or at the wrong VCore or whatever if there was a problem there. BTW there
is a part in the spec sheet saying it's there to make sure the VID signals are ok and ready to sample -- question is why does the CPU have to know (by means of the
input pin vtt_pwrgood), since the VID signals are sampled by the VRM.
Can't recall where I read that, but I think the PWRGOOD signal on the CPU (AK26) is there for the CPU itsell to know about VCC being stable (without spikes, swings etc) enough to turn some
CPU internal stuff on. Perhaps this is the same for vtt_pwrgood -- and that's not mentioned in the datasheet...
@Spajky2
Thanks for the input!
I'm wondering what they do exactly with these TVCs since it seems to have only room for 22 "bits" or data lines (so it's not enough to host all AGTL I/O pins). On a PPGA / FCPGA adapter that could just mean they put the few signals that changed going from PPGA to FCPGA thru the TVC -- but Powerleap seem to use the thing as well? Can you check to what signals the TVC is actually connected?
Perhaps the problem with some slotkets (including the generics) is something else. Here's a bit I that I found in "Intel® 815E Chipset Platform
For Use with Universal Socket 370 Design Guide " (Intel doc # 298350-001":
"Processor pin AG1 requires additional attention since it is a ground pin on a Pentium III processor
(CPUID=068xh) / Celeron processor (CPUID=068xh) and a VTT pin on a future 0.13 micron
socket 370 processor. A separate switch controlled by the TUAL5 reference schematic signal
determines whether pin AG1 is pulled to ground or VTT. Refer to Figure 11 for an example
implementation. "
That's only one of the differences. There are a few more of this kind, and perhaps one of them is the reason for the "no show" condition on some slotkets.
