which speed is better? 2000/1600/1333? check out the results!

[Evilsizer]

I was reading the intel papaers on QPI earlier and although 1156 has QPI Link arch in it... it never said exactly what it is used for. I would assume connecting the different cores and IO buses (PCIe and DMI) (Actual it is registered as PCI BUS 0 device 16 :S)

Considering it does everything and talks to the NB on the X58 platform I can only assume that it is similar on p55... except there is no "NB" on p55 since the pcie and southbridge IO is integrated to the CPU....

Sounds exactly like HT on amd.

i might be a bit behind on current tech. though i never recall intel putting the SB on the cpu. all the SB got put into the PCH when the memory controller and the PCIE 2.0 lanes got added to the cpu. the PCH from the diagram does still show PCIE lanes but i think it was you or someone else in the past. that pointed out the BW listed on the diagram seems to indicate that its only PCIE 1.0 on the PCH.

*thought i lost my post, so i added this in too*
except the cpu has no SB functions on it, its all in the PCH now. since intel moved prolly two of the largest chunks to the cpu, IMC and PCIE 2.0 lanes. i dont see anything on cpu layouts of any SB functions on the cpu.

Yeah the location of the L3 on P55 surprised me greatly, i had always assumed it was in the IMC, but then there it is shown in the CPU. Maybe the QPI links L3 to IMC?

All i really know for a fact is that faster QPI* = faster benchmarks. Beyond that it's guesswork based on articles out in the wild.


* or whatever the QPI setting on gigabyte p55 mobos actually does.

well if the EE's did really follow the KISS approach with regards to IMC vs on-package. then it should be connected directly, meaning either thru the L3 or side connected. not thru the QPI or DMI buss since that well the DMI anyways would limit things.

i was never tring to suggest that QPI wasnt faster for benching or well gaming. with this buss it really is scalable in two ways.. since the ratings are in GT/s which is just the number of data transfers per second. intel could have simply increased the width of the pipe to handle more, they could have also just increased the speed. they could do both at the same time if they wanted.

That is interesting that GB has a QPI setting, i wonder if they are interchanging the names. that was they dont confuse the customers, when it comes to increasing the buss speed. i mean CPUZ has the same thing, it lists QPI speed for LGA1156 cpus even though its DMI.

i just wish there was someone that could really clear this up... yea i posted before getting some sleep. i was up watching Haven and Eureka..

 

[Bobnova]

It's worth noting that i'm talking about the dual core 1156 stuff, the quad core has the IMC on-die.

I'll have to look at what other mobo manufacturers have for settings and see if QPI is listed.
There is something funky about dual core 1156 memory, the 8x multiplier is terrible, i suspect it's that at that multi the memory and the QPI (or whatever connects IMC to L3) don't match up for beans.


According to this:
http://www.anandtech.com/show/2901

PCIe is in the IMC (still a NB, just on-package IMO) along with the graphics and the memory controller, and QPI is the link between on-package NB and CPU.
Anandtech is usually pretty accurate about Intel stuff, but seeing as it isn't an Intel document we still have to take it with a grain of salt.

 

[Archer0915]

They say a picture speaks a thousand words, so.....

It seems on X58 his claim has some weight to it

Not trying to be a butthead but those are synthetic memory tests and pretty much just show how fast thing can move in and out of memory. The true tests are using compression and encode-decode -transcode as well as a little rendering.

 

[Grnfinger]

Not trying to be a butthead but those are synthetic memory tests and pretty much just show how fast thing can move in and out of memory. The true tests are using compression and encode-decode -transcode as well as a little rendering.

Oh I agree, no offence taken. It was a quick reference to see if there was merit to his (OP) argument.
I'm kinda glad I stumbled upon this thread, ram clocking is my weakest area, Evilsizer and Bobnova have shed some light.

It's worth noting that i'm talking about the dual core 1156 stuff, the quad core has the IMC on-die.

I'll have to look at what other mobo manufacturers have for settings and see if QPI is listed.
There is something funky about dual core 1156 memory, the 8x multiplier is terrible, i suspect it's that at that multi the memory and the QPI (or whatever connects IMC to L3) don't match up for beans.


According to this:
http://www.anandtech.com/show/2901

PCIe is in the IMC (still a NB, just on-package IMO) along with the graphics and the memory controller, and QPI is the link between on-package NB and CPU.
Anandtech is usually pretty accurate about Intel stuff, but seeing as it isn't an Intel document we still have to take it with a grain of salt.

Asus Max III has no QPI option, they did however add LN2 support

 

[Neuromancer]

i might be a bit behind on current tech. though i never recall intel putting the SB on the cpu. all the SB got put into the PCH when the memory controller and the PCIE 2.0 lanes got added to the cpu. the PCH from the diagram does still show PCIE lanes but i think it was you or someone else in the past. that pointed out the BW listed on the diagram seems to indicate that its only PCIE 1.0 on the PCH.

I said SB I/O I should have just said DMI bus

(DMI is the BUS that connects NB and SB... moving DMI bus to the CPU means the CPU talks directly to the SB. Hence referring to it as SB I/O)

Simple terminological error on my part. Will be more specific next time.