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geko said:
I already have the vcore as low as it can go before it becomes unstable...
The bolded sentance is confusing and making it hard for me to understand exactly what you are trying to say. If I am reading it right, you seem to be saying that the chip designers slow down the speed of each pipeline stage (by increasing the number of cycles an instruction will stay in the stage) to some "lowest common denominator". This makes sense, but there are some stages of the pipeline (for example, Fetch) that don't seem possible to predict the amount of time they'll take. If the data for a Fetch is in L1, you've got a cycle or two wait. If it's in L2, you've got 3 or 4 cycles. If it's in main memory, you've potentially got dozens of cycles. Paged to disk, and we're talking thoudands or more cycles. While they probaly do "size" each pipeline stage to some specific number of cycles, I don't think they nesscesaraly base it off the worst case scenario (since I doubt they're waiting 1000 cycles for each pipeline stage just in case they need something that has been paged). Should an instruction take longer than expected, the pipeline just stalls.
it's all about hunting for that sweet spot. I don't know, I guess I was trying to not be too technical about it...
He means as heat increases the resistivity of the interconnects increase and hence a decrease in electrical efficiency. Also more resistance = higher heat output, so an overheated component is converting electrical energy to heat energy.
If what ou're talking about is electromigration, you are a little off. "voltage" isn't leaking to neighboring wires, neither is current. The "wires" (interconnects, in a cpu) actually end up moving due to momentum transfer form electrons. Here's a great link:icesaber said:
There is some work being done on clockless processors. I know Intel did some a while back, and I think Sun is working on it now. You have to add in additional circuitry to synchronise some things, but you end up getting a faster processor by letting some tasks complete faster than they otherwise would have.icesaber said:The case of a memory fetch, write etc are a special case. You are indeed correct, a fetch will stall an instruction for a given amount of time depending on where the fetch is from. My intent was to show that generally speaking, in the case of an operative stage of the pipeline, the speeds of the other stages are generally based on the slowest one. If you want to get really technical, some of the stages are actually longer stages split over a period of time, but the circuitry needs to be designed to handle that. You can't have a stage that is wired to run in one clock cycle run in two just because it will take that long, it will instead give unexpected outputs.
Some engineers would actively split the 10 unit time I gave into two seperate 5 unit intervals, so that the new longest cycle time was actually 8. However, introducing a new stage introduces another interlock penalty, so in effect it could potentially worsen performance. Such is the nature of electrical engineering
All stages in the pipeline (other than a fetch/write) are given the same amount of time to complete because we're working with synchronous machines. The way the timing is handled is generally the worst case scenario, depending on headroom; the headroom is extra time left during the cycle after the stage has actually completed its work. Overclocking effectively reduces the headroom available, and eventually you will find the limit of the particular chip when you not only run out of headroom but start reducing the amount of time available for the stage's work itself to complete. Then, the stage is unable to complete and 'interesting' errors will likely (almost guaranteed, actually) occur.
I'll edit later tonight, I have to leave for work shortly.
peace.
