Just as another drop in the bucket...
L1 is typically split up into instruction cache and data cache (output).
Cache control and efficiency is actually more important than the overall size, but the differences between AMD and Intel's cache controllers aren't publicly available, and I have no clue about the details at the moment since I haven't read up on that stuff lately. I do know that keeping the cache filled with pertinent data is based on, as above, spatial locality, and repeated use. (It's also kinda cool how the cache controller works, but that's beyond the scope of this forum.)
The bigger a memory gets, the longer it takes to access it. This is one reason why L1s don't get bigger all the time, since they need to run fast to keep up with the flow of instructions and data.