Currently (Mar 2003), most modules are using 32Mx8 = 256 Mb DRAM chips, regardless of speed (6ns, 5 ns or 4.5 ns).
Each 256 Mb DRAM chip is organized as 32Mx8. There are 8 bit I/O per chip. 8 DRAM chips form a bank. A module with one bank or two banks has 64 bit I/O (8 Bytes).
For current AMD MB, maxMemoryBandwidth = fsb x 2 x 8 MB/s
x 2 is because of DDR (double data rate), i.e. data are transferred at both the rising and falling edge of the memroy clock
x 8 is because there are 8 bytes or 64 bits transferred at each cycle
E.g. at fsb = 166 MHz, maxMemoryBandwidth = 166 x 2 x 8 = 2656 MB/s (called PC2700)
at fsb = 200 MHz, maxMemoryBandwidth = 200 x 2 x 8 = 3200 (called PC3200)
For Intel P4, the fsb is quad rate, i.e. the fsb is running TWICE as fast as the memory bus speed at DDR.
maxMemoryBandwidth = fsb x 4 x 8 MB/s
E.g. at fsb = 166 * 2
memory bus = 166 (DDR 333, PC2700)
maxFSBandwidth = 166 x 4 x 8 = 5312 MB/s
Dual channel, memory module bandwidth = 2 x 2656 = 5312 MB/s
(but there is an overhead in running dual channel, eff BW ~ 4000 MB/s)