emory Training
There are multiple clocks in a system (CPU, IMC, memory, etc.), with a variable tick/tock initialization from start-up to start-up, a wide variety of signal pathways and variable environmental parameters, all of which combine to create a disparity (a skew) in the real arrival time of various signals at their destination. The pre-boot DDR calibration sequence introduces various delays between signals in order to achieve synchronicity. This is where DDR training kicks in; there are a number of patterns (either preset/provided by vendors, or custom-made) that test various signal/delay sets for the best possible ranges of these values. The accuracy of these delays determines the RTL/IOL, and ultimately influences memory performance. Since RTLs and IOLs are set at boot, training has a very real impact on the CAS latency.
Fast Boot settings either skip the memory training entirely, or use a very rough-and-ready form of training. While this is good enough for normal purposes, the best possible training sequence (determined from literature, or comparing the RTL/IOL values resulting from using each test, or in the absence of additional data, using the sequence that takes the longest time) should be used when fine-tuning memory parameters or benchmarking, because the variable signal/delay accuracy from a sub-par training regime makes parameter comparison questionable. Still, if enthusiasts are looking for moderate increases in memory performance, this step is generally optional..
