More options explained
CPU Vcore
Normal CPU voltage.
CPU Termination (CPU VTT)
VTT is the termination voltage. It is also the voltage VREF is derived from. System Bus Input Supply Voltage, often referenced as FSB termination voltage (VFSB) simply the voltage the fsb is running on. VTT is the termination voltage for data lines used to interface the MCH with the CPU die(s) via the Front Side Bus. Higher values can provide additional FSB overclocking margin, especially with 45nm dual-core processors and quad-cores CPUs in general. We have never found any additional gains to be had above 1.36 when using air- or water-cooling. Setting Auto should default to 1.10V for 45nm CPUs and 1.20V for 65nm CPUs. The VTT helps stabilize the signaling between the NB and CPU cores. Never should be bigger than CPU Vcore.
CPU PLL Voltage
The PLL voltage is essentially the voltage applied to the CPU's internal clock distribution system. Selecting a higher PLL (phase lock-loop) voltage may help the installed CPU clock higher or may assist with maintaining stability when operating at higher FSB speeds. Most users will find they do not need to set this to anything above 1.50. Exercise caution when experimenting with higher values as there have been reported cases of CPUs losing cores after being subjected to voltages in excess of about 2.00V.
CPU Reference (CPU VREF)
Nominal GTL reference voltage for current generation processors/chipsets should be about 2/3 of VTT (or approximately 0.8v), although you may find your board's values a little lower (~0.75v). Intel's GTL specification dictates that each reference voltage should be tightly controlled as 67% of the current VTT voltage (0.67 times CPU VTT Voltage). Historical data has shown that dual-core CPUs (in particular 45nm dual-cores) often clock to higher FSB levels when the GTL reference values are closer to 63 ~ 64% of VTT while quad-core CPUs usually need the full strength value or even a little more voltage (67 ~ 70% of VTT).
MCH Core Voltage
MCH Core voltage is your Northbridge Voltage (Memory Controller) and the amount needed to be set depends on a few things. It depends on the FSB you are running, the Strap you are using, the actual Memory Multiplier you are using (Ram Speed) and the amount of physical Ram installed. P45 MCH is a bit tricky as well, sometimes when you think you need more less would be better and visa versa. All of course depending on the other mentioned items above.
MCH Reference
The NB (SPP) GTL reference voltage provides the same functionality as those for the CPU, the only difference being that the Northbridge uses only a single value. Tuning in the right GTL reference voltage (usually near the nominal 67% value) can sometimes lead to lower stable VDIMM requirements.
CPU clock drive/skew
In simple words, they alter the pattern of the current traveling to the CPU and PCIE bus respectively. They are only really used for extreme overclocks where high voltages don’t provide a regular current to the CPU or PCIE. At the blistering speed that today's components operate at, timing issues can rear their ugly heads when trying to communicate with each other and result in instability, particularly when overclocking. To keep the different parts working in sync, some motherboards -- such as this one -- allow you to introduce tiny delays in different subsystems of your PC. In this case, you're 'skewing' the speed of the CPU clock as measured in picoseconds (ps), or one trillionth of a second. Increasing from default 800mV to 900 can help to stabilize system after overclock.
MCH Frequency latch and SPD
Your north bridge has an internal clock speed and latencies just like your CPU and memory. The FSB of your north bridge can be found by dividing your original CPU multiplier by your set CPU multiplier and then multiplying by your FSB.
So if you are running a E6600 (266 * 9) at 400Mhz x 8 your NB FSB is:
(9 / 8) x 400 = 450Mhz FSB (1800Mhz Total)
Just like your memory may be able to run at 4-4-4-12 at 1000Mhz but needs to run at 5-5-5-15 at 1200Mhz, your north bridge has a series of latencies which it must adjust in order to maintain stability at its FSB. These latencies seem to play a far more significant role in system performance than memory latencies.
Intel has predefined specific latencies at specific NB FSB speeds. They are referred to as straps. There is a strap for when the NB FSB is 1066Mhz and under, 1333Mhz FSB and under, 1600Mhz FSB and under, ect. When you go from the 1066Mhz FSB strap to the 1333Mhz FSB strap, the north bridge's internal latencies loosen to allow for greater stability. For most of us the challenge will be to see if you can get on/stay on the 333MHz strap with an FSB over 400MHz and still have good timings and memory speed with a low tRD. Sometimes a very difficult balancing act to pull off, many times just not possible. In other words the trick is to stay on as low of a strap as you can but still have your FSB and memory where you want it.
Set on auto or at 400MHz to allow looser timings if you overcloak.
Static Read Control Delay (tRD)
When it comes to overclocking, the MCH functions as a hybrid of sorts. Like a CPU, it has an upper frequency limit and more voltage can often raise this limit. On the other hand, since it interfaces with memory it also behaves somewhat like memory with internal "timings" whose absolute values derive from the established FSB.
The outside world's first introduction to variable tRD settings came when a few overclockers noticed that setting lower MCH "straps" allowed for higher memory bandwidths. What they didn't know at the time was that they had unintentionally stumbled upon tRD. Tricking the motherboard into detecting an installed CPU as an 800 FSB (200MHz) part forced the MCH into setting a lower tRD value than if the FSB were 1066 (266MHz). Consequently, overclocking the system to the same higher FSB value with the lower strap setting yielded higher memory performance. Often times the effect was significant enough that real-world performance was higher even with a lower final FSB. The tradeoff was apparent however: a lower strap meant a lower maximum FSB. The MCH tRD value, just like a memory timing, must eventually be loosened in order to scale higher. What's more, as is the case with memory, additional voltage can sometimes allow the MCH to run with tighter "timings" at higher speeds.
Eventually the inevitable next step in memory performance tuning became a reality. The option to adjust tRD independent of MCH strap selection became part of every overclocker's arsenal. Nowadays the MCH strap setting does little more than determine which memory multiplier ratios are available for use. Although tRD adjustments are now possible in many BIOS implementations, some motherboard manufactures choose to obfuscate their true nature by giving the setting confusing, proprietary names like "Transaction Booster" and the like. Don't let these names fool you; in the end they all do the same thing: manipulate tRD.
Advanced literature
http://www.thetechrepository.com/showthread.php?t=87
http://edgeofstability.com/articles/dfi_p35/gtl/gtl1.html
