- Joined
- Mar 7, 2008
I know the posting date, but this information is from before this. I only just saw it now and posting, ok?
In short, in recent days there was MemCon event where the below was originally shown:
The concept is not that challenging. You take two ranks on one module, and instead of accessing them one a time as you do now, you get data from both simultaneously. A buffer chip is used to interface this.
This might be for servers at first, especially with the buffering. You get "up to" double the bandwidth for a module at a possible cost to latency. Implications if you follow through are this could only be available at capacities that are already 2R (32GB?) so you're probably not getting lower capacities. I also wonder if it is possible to have "4R" modules, to in effect have dual 2R operation within one module. All else being equal, 2R modules generally performs better than 1R.
This is a bit like increasing the number of channels, but within module. The higher speed data transfer from module to memory controller could be a challenge, and I think this would become the main bottleneck instead.
In trying to dig up more on this, I found the following link: https://www.prnewswire.com/news-rel...s-fastest-server-memory-module-301697691.html
Last year SK Hynix are talking about what they call MCR DIMM. It sounds very much like MRDIMM but I'm not sure if it is exactly the same thing with a different name, or if there is more of a difference. MRDIMM might be the JEDEC standardised version, since MCR DIMM sounded like a SK Hynix and Intel collaboration.
In short, in recent days there was MemCon event where the below was originally shown:
The concept is not that challenging. You take two ranks on one module, and instead of accessing them one a time as you do now, you get data from both simultaneously. A buffer chip is used to interface this.
This might be for servers at first, especially with the buffering. You get "up to" double the bandwidth for a module at a possible cost to latency. Implications if you follow through are this could only be available at capacities that are already 2R (32GB?) so you're probably not getting lower capacities. I also wonder if it is possible to have "4R" modules, to in effect have dual 2R operation within one module. All else being equal, 2R modules generally performs better than 1R.
This is a bit like increasing the number of channels, but within module. The higher speed data transfer from module to memory controller could be a challenge, and I think this would become the main bottleneck instead.
In trying to dig up more on this, I found the following link: https://www.prnewswire.com/news-rel...s-fastest-server-memory-module-301697691.html
Last year SK Hynix are talking about what they call MCR DIMM. It sounds very much like MRDIMM but I'm not sure if it is exactly the same thing with a different name, or if there is more of a difference. MRDIMM might be the JEDEC standardised version, since MCR DIMM sounded like a SK Hynix and Intel collaboration.
