Just to reiterate and perhaps restate what Bageland2000 mentioned...
Intel processors have a front-side bus that is a bit misleading. Intel says "1333mhz front side bus", but the reality is actually 333mhz clock rate with four data transmissions per clock. Hence, you get an effective data rate of 333 x 4 = 1333mhz.
Double Data Rate (DDR) memory works in a similar fashion -- DDR2/800 works at 400mhz clock rate with two data transmissions per clock. Hence, you get an effective data rate of 400 x 2 = 800mhz. Rinse and repeat for all other speeds, examples: DDR2/1066 (533 x 2) or DDR21200(600 x 2)
Next-to-last thing: Essentially every consumer motherboard on the market today has a dual-channel memory interface. This essentially boils down to the motherboard being able to read from two banks of memory simultaneously, thus doubling memory bandwidth in nearly all circumstances.
Very last thing: no current intel processors have an integrated memory controller like the AMD's do. All memory interface is done from the chipset northbridge, so it goes like this: CPU -> Northbridge -> RAM. When you select a certain memory speed, that will be the speed of the link between the northbridge and ram. When you select a certain FSB speed (ie, overclocking the CPU), that will be the speed of the link between the CPU and the northbridge.
Ok, are you ready for the conclusion?
FINAL EXAM ANSWERS
The link between your CPU and northbridge is determined by the FSB.
The link between your memory and northbridge is double the speed of the memory if you're using two sticks of ram (dual channel)
There is also a "ratio" component that determines how fast your memory goes versus the FSB. The only one you need is 1:1, and if you have questions, see the footnotes to this post.
So... Really really simple math time:
FSB = Memory speed * number of memory channels used (1 or 2 are the only options)
Examples of dual-channel motherboards and the necessary memory speed:
FSB: 1333Mhz
Memory: 667Mhz
FSB: 1600Mhz
Memory: 800Mhz
FSB: 2000Mhz (this is pretty close to the limit for most boards off-the-shelf)
Memory: 1000Mhz
So, in order to get the true benefit of your DDR2-1200 memory, you'd need to run an FSB of 2400Mhz. Unless you plan on some SERIOUS hardware (both in terms of cooling, modifications to the board, and power) then you'll never get your use out of them.
Footnote:
Many motherboards allow for memory speeds that are OVER the FSB speed, such as 5:6, 3:4, even 1:2. These technically allow the memory to operate at a faster clockrate than the front side bus speed. So then why doesn't everyone buy DDR2/2000 and have uber benchmark scores? Because if you're using more than one memory stick, it's effectively worthless
Here's why: Remember the FSB? This is the bus linking the CPU to the northbridge. All memory access MUST go through the northbridge on Intel processors (currently; this will change with Nehalem in '08).
So, for any memory access to happen, it MUST come from the CPU, across the front side bus, to the northbridge, and then to memory. Herein lies the problem: if you're running dual channel, then the front side bus becomes the bottleneck.
Think about it:
Front side bus at 1600mhz (it's a 400mhz clock rate underneath)
Memory speed at 800mhz (it's also a 400mhz clock rate underneath)
Two memory channels running in dual-channel mode.
In the above scenario, you capable of ENTIRELY saturating the front side bus with memory traffic. If you raise the memory speed to 1200mhz, it gains you nothing, because 1200 x 2 = 2400 which is still less than the 1600mhz front side bus.
You could raise the memory speed to a gazillion gigahertz, but so long as your front side bus is still at 1600mhz, your system speed really isn't going to budge. There are corner cases where you can see incredibly tiny gains (two percent or less) in tasks that do a LOT of very organized and linear memory address reads, such as un-raring absolutely massive files from within ram. This comes from the northbridge having a small amount of prefetch logic for these sorts of cases, but it's also offset by the lack of buffer and latencies in the asynchronous signal timings.