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So what's intel's response going to be to AMD's XXXx3D CPU's?
- Thread starter magellan
- Start date
We see Intel's responses for about two years, and in plans are only more e-cores and a higher boost/turbo clock (with some IPC improvements as usual). Well, it's more like for multithreading, Intel adds e-cores to stay in TDP, for gaming, they bump clocks. If I'm right then the next-gen will still have 8 p-cores, but higher boost clocks, improved IPC, and with e-cores, we will see.
If nothing will change then the next Intel gen will appear somewhere in Sept-Oct this year.
It's expected to see 14900KS sometime soon (some said it will be presented at CES). Leaks say it will have 6GHz or more on all p-cores. We will see as somehow I doubt it will keep it at the same or not much higher TDP.
If nothing will change then the next Intel gen will appear somewhere in Sept-Oct this year.
It's expected to see 14900KS sometime soon (some said it will be presented at CES). Leaks say it will have 6GHz or more on all p-cores. We will see as somehow I doubt it will keep it at the same or not much higher TDP.
AMD X3D.. at least AM4 is good for games, and low energy usage. 58X3D is super easy to cool. I mean its ok for clicking around the web too. For my next CPU I am leaning towards a 13700K or 14700K, and the board I have only QVL's to 6000 so not sure if that is a big deal or not. Probably not a big deal if it gets me in the door..
I wouldn't call it a niche product when only 7800X3D has significantly beat the sales of any Intel CPU in the past half year. There were articles about some large stores that were selling as many 5800X3D as all Intel 13th-generation retail CPUs in a few months. In about May-June reports were about 5800X3D, in Oct-Dec 7800X3D.
Intel is doing as much as it can but has nothing to beat these CPUs in efficiency in games. They use 2-3x higher TDP CPUs against AMD to match or slightly beat them in games. If Intel wasn't doing anything then we wouldn't see all those refreshes with bumped CPU clocks to the TDP limits and added pretty useless e-cores. I mean, who needs 8-12 e-cores for anything else than synthetic benchmarks at home?
- Joined
- Mar 7, 2008
Intel are coming to the end of their process node catch up plan. The next year or two should be very interesting once they have a competitive process to make their CPUs on. Arrow Lake is next for desktop and on process alone we're looking at potentially over 2 node jump vs current desktop. That can be split between efficiency and performance as desired.
X3D I see as a patch on fundamental limits in current CPU design, and for consumer use cases it primarily benefits gaming. There are many productivity use cases where the cheaper non-3D models outperform it. I'm sure everyone here is bored of me saying modern CPUs don't have enough ram bandwidth when pushed. On AMD's CPUs that's made worse by their internal connectivity bandwidth also. A large cache helps takes the edge off that.
X3D I see as a patch on fundamental limits in current CPU design, and for consumer use cases it primarily benefits gaming. There are many productivity use cases where the cheaper non-3D models outperform it. I'm sure everyone here is bored of me saying modern CPUs don't have enough ram bandwidth when pushed. On AMD's CPUs that's made worse by their internal connectivity bandwidth also. A large cache helps takes the edge off that.
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- Mar 7, 2008
As much as I'd love to see a large unified cache on AMD, which logically would be L4 at IOD, I doubt AMD will do that. At least not on consumer tier. It always comes back down to a cost vs benefit analysis. They think their offerings are good enough for most use cases. Cache at L4 could be slower, but may need to be bigger to compensate. GB scale HBM could be interesting there but it isn't going to be cheap. Such a L4 cache would benefit use cases where all cores are working on the same data and avoid slow trips back to ram.
- Joined
- Mar 7, 2008
I think the chances of AMD or Intel listening to a nobody like me are exactly zero. 5775C was a repurposed mobile offering they already had, to say they launched the desktop model. It had 128MB of L4 cache which is bigger than early X3D offerings. You could say X3D CPUs are "large LLC" just that the LLC is L3 instead of L4.
The cache is quite big and heats up everything around, so it's a problem for most CPUs. All higher Intel CPUs already have problems with heat and TDP. This is the difference between AMD and Intel. Where AMD drops down the clock but still works at its declared frequency range (even with a pretty standard cooler), then Intel drops down the clock more significantly and simply throttles below it much faster than AMD (even on an above average cooler).
If the L4 cache were so good, then it would be used, at least in the highest CPUs. AMD went with 3D cache instead, and it shows its limits. Intel sees bumping the core frequency as a better option. A large L4 cache is slow, and since everything uses some internal bus and frequency, then it would have to run at dividers to keep stability. Server CPUs are something else as they typically run at low frequencies, so it's easier to put a large cache inside.
If the L4 cache were so good, then it would be used, at least in the highest CPUs. AMD went with 3D cache instead, and it shows its limits. Intel sees bumping the core frequency as a better option. A large L4 cache is slow, and since everything uses some internal bus and frequency, then it would have to run at dividers to keep stability. Server CPUs are something else as they typically run at low frequencies, so it's easier to put a large cache inside.
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- Mar 7, 2008
In Broadwell-C the core die never got that hot outside of OC, and splitting it made heat removal easier. In a similar way Intel during their peak fab woe era while higher power than Ryzen was usually much easier to cool due to lower power density.
This is the thing. CPUs are designed to be best for most people at most things, at an economic price. While I have no doubt L4 on AMD would help with single socket multiple CCX designs, it would probably not be as cost effective for most. It may not be applicable for multi-socket systems/NUMA since the main advantage I'm pushing it for is having a unified cache.
If it is faster than ram (bandwidth and/or latency), it helps. My main complaint is consumer tier ram systems are incredibly slow.
I can't remember that far back in detail. I remember early systems where you literally added chips into sockets. Later on it moved to Cache On A STick (COAST) modules before CPUs got enough integrated cache for this to go away. In a modern implementation the wiring would be too complicated to do off package I feel.
OP
- Joined
- Jul 20, 2002
- Thread Starter
- #15
@mackerel
Super socket 7 motherboards had the LLC motherboard cache in soldered chips and in quantities up to 2MiB. The most powerful super socket 7 CPU, the Cyrix 5x86 only had a 16KiB write-back unified cache (i.e. for data and instructions), so the motherboard LLC was 128 times larger than the only on-chip cache. If they can incorporate HBM on a GPU interposer or GDDRx on a videocard I don't see why it would be impossible to integrate it on motherboards. Instead of using HBM maybe they could use high capacity, high speed GDDR6 modules. However, since the northbridge was the memory controller for super socket 7 it could keep track of memory accesses and manage the motherboard LLC but I think a modern CPU would have to directly control the external cache, which would mean even more I/O pins.
Super socket 7 motherboards had the LLC motherboard cache in soldered chips and in quantities up to 2MiB. The most powerful super socket 7 CPU, the Cyrix 5x86 only had a 16KiB write-back unified cache (i.e. for data and instructions), so the motherboard LLC was 128 times larger than the only on-chip cache. If they can incorporate HBM on a GPU interposer or GDDRx on a videocard I don't see why it would be impossible to integrate it on motherboards. Instead of using HBM maybe they could use high capacity, high speed GDDR6 modules. However, since the northbridge was the memory controller for super socket 7 it could keep track of memory accesses and manage the motherboard LLC but I think a modern CPU would have to directly control the external cache, which would mean even more I/O pins.
- Joined
- Mar 7, 2008
If you look at HBM implementations they're all located right next to whatever they're talking to. HBM is a very wide bus at 1024 bits, so imagine adding another 1000+ pins and wires out of the socket. Just can't see it happening. It pretty much only makes sense hard wired.
GDDR I'm less familiar with, but looking at GPU implementations we go up to 384 bit. Regular DDR is 64/bit per channel so at least here the increase in width isn't so bad. But this goes around to my other wish list item of more channels on consumer tier hardware. Quad channel memory would be 256 bit and not far off GDDR width (but not speed) while maintaining proven upgradability. GDDR is another ideally soldered close tech.
The other alternative is the console route. Just give up ram expansion and have soldered ram. High speed low latency, unified memory too with a big enough iGPU. We're not there yet, but there have been photos of Lunar Lake which is the next mobile offering from Intel. LPDDR5X-8533 so faster than anything standard DDR5 right now.
www.computerbase.de
GDDR I'm less familiar with, but looking at GPU implementations we go up to 384 bit. Regular DDR is 64/bit per channel so at least here the increase in width isn't so bad. But this goes around to my other wish list item of more channels on consumer tier hardware. Quad channel memory would be 256 bit and not far off GDDR width (but not speed) while maintaining proven upgradability. GDDR is another ideally soldered close tech.
The other alternative is the console route. Just give up ram expansion and have soldered ram. High speed low latency, unified memory too with a big enough iGPU. We're not there yet, but there have been photos of Lunar Lake which is the next mobile offering from Intel. LPDDR5X-8533 so faster than anything standard DDR5 right now.
Intel: Lunar Lake mit Memory on Package abgelichtet
Intels stromsparenden SoC-Lösung Lunar Lake sei noch für dieses Jahr geplant, erklärte Intels Michelle Johnston Holthaus zur CES 2024.
www.computerbase.de
OP
- Joined
- Jul 20, 2002
- Thread Starter
- #17
I see your point mackerel, if you're going to use GDDR as some sort of cache why not just use it in place of main memory.
I rarely bother upgrading the memory in my rigs anymore, I only replaced the memory once in the case of my last two builds (I re-used the DDR4 from my dead LGA-2011 build in my LGA 1151 build then upgraded to 32GiB) and I haven't swapped out CPUs in a given motherboard in my last three builds because the potential perf. delta was so small. If they did sell motherboards w/BGA CPUs and a decent amount of GDDR system memory that would work for me as long as they retained the ability to overclock core/memory.
I rarely bother upgrading the memory in my rigs anymore, I only replaced the memory once in the case of my last two builds (I re-used the DDR4 from my dead LGA-2011 build in my LGA 1151 build then upgraded to 32GiB) and I haven't swapped out CPUs in a given motherboard in my last three builds because the potential perf. delta was so small. If they did sell motherboards w/BGA CPUs and a decent amount of GDDR system memory that would work for me as long as they retained the ability to overclock core/memory.
