Why wait for Socket 939?

[autoMATTic]

......but what I do think could be cool is the Duron-754. Even if it isn't 64-bit the onchip memory controller should CREAM the Celeron.

Thought I was the only one who knew about this chip. I wonder if it will be able to outdo a P4. The current Athlon Xp sure do give a P4 a run for the money and this chip is sure to be better than a Athlon XP.

 

[c627627]

There's no such thing as a Socket 754 Duron (yet)

There are Paris and Palermo cores of 754 with just 256 KB of cache and no AMD64 support that are rumored to be released in the second half of 2004.

It would make sense for AMD to use those cores when and if they release them to counter the upcoming Prescot-256 Celeron D.

Maybe they'll call them Duron, maybe not, but with Athlon XP prices being affordable for such a long time, there were always better alternatives to Celerons.

 

[OC Detective]

The benefits of the dual channel are expected to balance out the loss of the cache indeed I think AMD might even rate a similar speed 512KB L2 cache cpu on dual channel (939) higher than a single channel 1024KB L2 cache 754.
Edit - another theory worth exploring is whether you can overclock a cpu with smaller cache (512) further than the one with larger cache (1024) as with the scaleability of these cpus the extra Mhz gained might negate the loss of cache - this is only a theory and I have no proof whatsoever to back it up!
The Barton v Tbred comparison could only be used I guess if it was desktop v desktop but even then the scaleability of these models is not as good as the 64's.

 

[c627627]

I think AMD might even rate a similar speed 512KB L2 cache cpu on dual channel (939) higher than a single channel 1024KB L2 cache 754.

Just about everyone expects 2.2 and 2.4 parts to have a higher PR rating at 939 than at 754 even if 939 is half the cache...

Hey OC D, May 25, 3800+ or 3500+ or both?

If I were a betting man: 3800+ 939 at wallet breaking markup... place your bet now

 

[hitechjb1]

...
939 has twice the max memory bandwidth of a 754 due to the 128-bit memory bus in 939. This is in additon to the dual channel memory controller in 939. For applications that require constantly changing, large, and well structured spatial data as in scientific computations, video encoding/decoding, image processing, ..., these applications would be benefited directly from the 128-bit memory bus of 939 (vs the 64-bit of 754), .... Since data needs to be refreshed constantly from the main memory (L3) to the on chip L2 via the memory bus as size of data >> L2 size at any given time.

Interesting question: how would the following A64 perform running the same CPU frequency, memory bus frequency and HT bus frequency
A - A64 1 MB L2, 128-bit memory bus (939/940)
B - A64 1 MB L2, 64-bit memory bus (754)
C - A64 512 KB L2, 128-bit memory bus (939)
D - A64 512 KB L2, 64-bit memory bus (754)

A is better than B or C.
B or C is better than D.
Between B and C, it depends on applications. For memory intensive applications, C has an advantage.
(My choice would be C (512 KB L2 939) at first to save money on CPU, then upgrade later to A (1MB L2 939) when CPU yield mature and price lowered.)


Recap on 939 memory latency, memory bus bandwidth and system bus bandwidth:

For the A64 CPU, the memory traffic and the traffic for the rest of the devices (video, IDE, SATA, serial links, ...) are separated at the CPU rather than at the chipset (NB). As a result,

- The average memory latency between the CPU (after L2 miss) and the memory (L3) is reduced.

- The effective bandwidth of the A64 memory bus (128-bit in 939) to/from the CPU is alone higher than the effective P4 memory (and system) bandwidth (estimated about 15-20% higher), and almost twice that of XP and also that of 754 (estimated 81-89% higher).
(See earlier post on memory bandwidth.)

- The max combined system bus bandwidth of memory bus (in 939) and HyperTransport in an A64 system is more than twice the sytem bus (FSB) of a P4 system and four times the system bus (FSB) of an XP system.
(See earlier post on system bus bandwidth.)

Estimation and importance of 939 platform memory bandwidth (page 19)

Differences between the XP FSB and the A64 buses (separate memory bus and HyperTransport bus) (page 19)

Some remarks on cache latency, cache size, memory latecny and memory bandwidth (for A64's) (page 19)

 

[OC Detective]

For me it kind of depends on what Intel are doing as well. As AMD are the market followers and not the market leaders - if Intels prices stay around what they are just now I really dont see AMD marking up their top of the line by much more than what they are at present (USD417?)- especially as they still need to keep a differential between the FX and A64 models. Depends on what your definition of wallet breaking is - if they release a 2nd tier 3500+ at say USD275 - USD300 (assuming a 3800+ is released as well) I would be happy to buy it. However AMD might also be happy to release just a 3500+ initially at current USD400+ levels and get say a couple of months out of higher ASP's before releasing a 3800+ and making that at the 400+ level with the 2nd tier 3500+ then dropping to sub 300 levels and others in the 754 category dropping as well. Again all speculation and I would say entirely marketing not operations driven. (By that I mean they probably could release a 3800+ but may decide not to because:
A. Intel may not have a comparitive product out at a similar rating
B. Now the turnaround is just about complete - the corporate objective of driving up ASP's at least cost whenever possible.

 

[c627627]

hitechjb1's post shows how nice it would be to go 939 instead of 754 but $500 is wallet breaking and so is $450 when compared to what Socket 754 can do.

Even if 939s are "only" $399 which they won't be IMHO, remember, 754 at just 2.2 GHz is like Athlon XP at 2.8 GHz roughly speaking,

so what then is 754 at 2.6 GHz or 2.8 GHz:
http://www.ocforums.com/showthread.php?s=&threadid=288589

 

[mittlesmertz]

Sorry, but you're wrong...
Check out these benches:

http://hardocp.com/article.html?art=NTc1LDQ=

The only difference between the 3000+ and 3200+ is 512K L2, and there is a very noticeable difference. 700 3kmarks is noticeable in my book, justifying the extra 200+ in the 3200+ rating....

I'm curious about this comparison.
If I read the link right, they ran the comparison in 3dMARK2001 at the lowest resolution (800X600).
For fun I ran my Athlon64 3000 at those settings and posted
21,870 at stock settings for the CPU and videocard.
the link doesn't list the rest of the test system, but I am consistently running over 20,000 in
1074X768 32bit resolution with a 20 point increase in the FSB.; in stock form at the high resolutions I posted 19,604.

I purchased my 64-3000 on Newegg for $208.00. I agree that 700 D-Marks is a noticeable difference.
That's why I'm glad I saved the $ and bought the 3000!!!

 

[Maxvla]

Not one PCI locked nForce3 150 model has been reported here.

not true. my shuttle AN50R can go up to 338fsb and i'm able to use my creative sound blaster audigy pci card to listen to music no problem at what would be nearly 56mhz pci. no way i could do that with a non pci locked mobo.

 

[OC Detective]

I also heard the AOPEN model was locked as well?

 

[Maxvla]

I also heard the AOPEN model was locked as well?

i think that was proved innacurate.

really though it seems to be random. some boards have it, some don't. its pretty odd.

 

[Maxvla]

i'm using my komusa pc4200 up to 301mhz, after that its 5:4.

 

[c627627]

http://www.lostcircuits.com/motherboard/nforce3_pci/

We used the Shuttle AN50R nForce3 -150 based board to monitor the PCI input clock at different frequencies using a HewlettPackard HP54512B High Spee3d oscilloscope. Here is what we found:

At 200 MHz system clock, one PCI clock peak to peak interval equals exactly 30 ns, which corresponds to 33 MHz. At 222 MHz, the clock cycle time gets shorter, in fact, we measured 27.1 ns which corresponds to 36.9 MHz.

Our measurements clearly show that, also on the nForce3 chipset, the PCI bus frequency is directly derived from the system clock by means of a divider.


EDIT: However, AOpen AK89 Max does have a confirmed PCI lock:
http://www.ocforums.com/showthread.php?s=&postid=2709350

 

[tekOC]

I think I'm fine with my main Intel rig for a while.

When I really need to I'll get Socket 939, and sell my Socket A AMD rig

 

[Speed_Mechanic2]

The PCI/AGP divider issue is a issue between motherboard makers and nVidia. There have been referance design motherboards with the nForce3 150 chipset that have showned a locked PCI. nVidia hasn't backed down from stating that the AGP/PCI can be locked with their nF3 150 chipset. But most nF3 150 motherboards would fail a Geiger Test.

 

[bulk88]

What I've figured about NF3 150's pci lock is that, it exists, and that Nvidia didn't document it or gave it a wrong definition or left it marked reserved.

I think what happened was Nvidia's datasheets writers knew there was a PCI lock but didn't know how to turn it on so they said to themselves, "the HTL will always be 600mhz because of the HTL multi, so I guess the HTL multi makes a PCI lock since the PCI is ratioed off the HTL", so they wrote down, to turn on the PCI lock set (making up) register 10 to 1 (effectivly turning on a /18 divider). Now some MB bios designers may have found out on their own (they have the equipment to check the PCI bus dont they? lol) or from another document the PCI divder table, so some bioses automatically use a higher divider when you overclock or lowers the HTL multi when you overclock.

Now we know some boards do have a PCI lock, I think in those boards the BIOSes properly turn on the lock, which is a differnet register than the official one. Also clockgen probably also turns this register on enabling the PCI lock.