A little about RAM

[Anonaru]

Well, I'm a long time envelop-pushing chip-torturing Oc junkie from another overclocking community-- I'm looking to make a home here too! Right now I'm running a C2 Phenom II at 3.85Ghz (4.0 is basically chernobyl waiting to happen, even on my H100), and I've also gotten the newer FX-8320 stable at 5.03GHz (But run it at 4.65). Also have a sandy bridge i7 pretty high up there (4.89GHz I believe it was last), anyways!

I have a question concerning RAM. Obviously the function of the big 4 in timing is pretty obvious. You know, your 9-9-9-24, etc. I also understand that higher frequency reduces latency and speed, but tighter timings are vital as well.

My question is, what impact do all of the other CLK settings have on RAM performance? I run my RAM (On my Phenom II rig) at 1742MHz at 9-9-9-20-28-1T, which is as good as it will get on those numbers (It is G-Skill's non performance ram). I run the higher frequency due to a high FSB / NB increase. Does tightening things such as Precharge time have a noticable influence on performance? I've been able to change these settings, sometimes to their absolute minimum without much of an impact on stability. Some timing tightenings in these fields seem to increase performance, while others seem to actually slow the RAM down.

Research online seems to be a bit mixed, hoping somebody here has more practice / insight than me on this matter. Thanks!

 

[Woomack]

For daily pc tightening sub timings on AMD platforms will give almost nothing. They have so slow memory controllers that the only way to make them faster ( and see it at least in benchmarks ) is to set higher CPU-NB and keep low main timings.

You can of course try some settings but it's generally waste of time if you are not going for best Spi32m time .
There is no special rule how to set sub timings as all depends from board and memory itself.

I can only say that there is point to play with sub timings with 1155/IB and new memory kits 2133+. Main reason is that most available IC are not letting to set tight main timings and most memory kits have really loose sub timings set in profiles ( so they are compatible with almost all boards available on market ).
At least on this platform ( IB ) good sub timings can give you up to 1-2GB/s higher transfers what is still not that much when read transfers for ~2400MHz kits on overclocked cpus are above 25GB/s.

 

[Anonaru]

For daily pc tightening sub timings on AMD platforms will give almost nothing. They have so slow memory controllers that the only way to make them faster ( and see it at least in benchmarks ) is to set higher CPU-NB and keep low main timings.

You can of course try some settings but it's generally waste of time if you are not going for best Spi32m time .
There is no special rule how to set sub timings as all depends from board and memory itself.

I can only say that there is point to play with sub timings with 1155/IB and new memory kits 2133+. Main reason is that most available IC are not letting to set tight main timings and most memory kits have really loose sub timings set in profiles ( so they are compatible with almost all boards available on market ).
At least on this platform ( IB ) good sub timings can give you up to 1-2GB/s higher transfers what is still not that much when read transfers for ~2400MHz kits on overclocked cpus are above 25GB/s.

Holy hell, you just took my question and suplex'd it- Bravo good sir! I was afraid of this-- Really, cranking up my NB is really all that makes a noticable change in performance on my PII. If there's no set rule, I'll poke around until I get a good mix of performance at a lower voltage than I'm runing now-- Thanks a ton!

 

[Weatherlite]

I've been doing a LOT of reading lately on memory and must say that it's DAMN confusing! lol I've even tried reading technical papers from Micron. I honestly don't know if there is a definitive answer out there which is accesible to the common Joe like us. I did find this tidbit which was written in the heyday of DDR2, but was updated and is supposed to still apply to DDR3. However, it was noted that it will differ from board to board, AMD vs Intel, and is minimal due to the very high transfer rates on DDR3, like Woomack said. But, here it is anyway.

tCL:
Large influence on stability / Medium influence on bandwidth
From CAS 5 to 4 results change ~5-10mb/s. The same change will most likely be seen when going to CAS 3. This timing is widely seen as most important (Command rate disregarded).
Recommendation: 4 for normal usage, 5 when oc"ing. Tweaked: 3.


tRCD:
Medium influence on stability / Large influence on bandwidth
tRCD going from 4 to 3 gives ~15mb/s. From 5 to 4 also yields 10-15mb/s. This timing is considered second important after CAS, but actually it"s more important on 680i/DDR2.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRP:
Medium/small influence on stability / Small influence on bandwidth
Results vary close to nothing when changing from 3 to 4 to 5. Still this timing needs to finish its cycle before a new one starts, so dont set it higher than 5.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRAS:
Small influence on stability / Small influence on bandwidth
tRAS seems to act differently on integer/float results. Integer, going from 15 to 10 changes by ~5mb/s. Float doesnt change.
tRAS is an "end-timing", so dont go to high. And not lower than what tCL+tRCD equals.
Recommendation: 12 for oc/normal usage. 15 if you want to push mhz. Tweaked: 8


tRRD:
Small influence on stability / Small influence on bandwidth
tRRD of 2 didnt change the results. Nor did a tRRD of 4. This is a delay-timing so a too low value may result in recalculation.
Recommendation: Auto for oc/normal usage. 4 if you want to push mhz. Tweaked: 2


tRC:
Medium influence on stability / Large influence on bandwidth
This timing is quite surprising. Going from 30 to 21 gave ~90mb/s. From 23 to 21 gave ~15-20mb/s.
tRC is last timing before ram burst (data transfer).
Dont set too high. And tRC should be greater than tRAS + tRP or you might get corruption.
Recommendation: 21 for normal usage. 30 if you want to push mhz. Tweaked: 15


tWR:
Small influence on stability / Small influence on bandwidth
Small change from 6 to 3. Setting timing too low will cause ram to fail switching to "read mode".
Recommendation: Auto for oc/normal usage. 6 if you want to push mhz. Tweaked: 3


tWTR:
Large influence on stability / Small influence on bandwidth
From 10 to 8 didnt change results. 6 would lock up the system. This timing gives no bonus but affects stability a lot. Use with care.
Recommendation: Auto for oc/normal usage. 10 if you want to push mhz. Tweaked: 8(7)

tREF:
Small influence on stability / Small influence on bandwidth
Changing to 3,9us didnt show improvements in benchmark. It also didnt seem to affect stability. tREF was important with DDR1.
Recommendation: Auto for oc/normal usage. 7,8us if you want to push mhz. Tweaked: 3,9us


Command Rate:
Settings are 2T/1T. You probably already know a lot about this timing.
The 680i struggles running 1T above 800mhz. So do the ram - atleast 2,2v are needed. This timing gives a great boost to bandwidth, but is fairly hard to attain. I wont recommend any setting regarding this timing. You need to find what mhz you get with 1T, then find mhz with 2T, then compare benchmarks.

 

[Anonaru]

I've been doing a LOT of reading lately on memory and must say that it's DAMN confusing! lol I've even tried reading technical papers from Micron. I honestly don't know if there is a definitive answer out there which is accesible to the common Joe like us. I did find this tidbit which was written in the heyday of DDR2, but was updated and is supposed to still apply to DDR3. However, it was noted that it will differ from board to board, AMD vs Intel, and is minimal due to the very high transfer rates on DDR3, like Woomack said. But, here it is anyway.

tCL:
Large influence on stability / Medium influence on bandwidth
From CAS 5 to 4 results change ~5-10mb/s. The same change will most likely be seen when going to CAS 3. This timing is widely seen as most important (Command rate disregarded).
Recommendation: 4 for normal usage, 5 when oc"ing. Tweaked: 3.


tRCD:
Medium influence on stability / Large influence on bandwidth
tRCD going from 4 to 3 gives ~15mb/s. From 5 to 4 also yields 10-15mb/s. This timing is considered second important after CAS, but actually it"s more important on 680i/DDR2.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRP:
Medium/small influence on stability / Small influence on bandwidth
Results vary close to nothing when changing from 3 to 4 to 5. Still this timing needs to finish its cycle before a new one starts, so dont set it higher than 5.
Recommendation: 4 for oc/normal usage. 5 if you want to push mhz. Tweaked: 3


tRAS:
Small influence on stability / Small influence on bandwidth
tRAS seems to act differently on integer/float results. Integer, going from 15 to 10 changes by ~5mb/s. Float doesnt change.
tRAS is an "end-timing", so dont go to high. And not lower than what tCL+tRCD equals.
Recommendation: 12 for oc/normal usage. 15 if you want to push mhz. Tweaked: 8


tRRD:
Small influence on stability / Small influence on bandwidth
tRRD of 2 didnt change the results. Nor did a tRRD of 4. This is a delay-timing so a too low value may result in recalculation.
Recommendation: Auto for oc/normal usage. 4 if you want to push mhz. Tweaked: 2


tRC:
Medium influence on stability / Large influence on bandwidth
This timing is quite surprising. Going from 30 to 21 gave ~90mb/s. From 23 to 21 gave ~15-20mb/s.
tRC is last timing before ram burst (data transfer).
Dont set too high. And tRC should be greater than tRAS + tRP or you might get corruption.
Recommendation: 21 for normal usage. 30 if you want to push mhz. Tweaked: 15


tWR:
Small influence on stability / Small influence on bandwidth
Small change from 6 to 3. Setting timing too low will cause ram to fail switching to "read mode".
Recommendation: Auto for oc/normal usage. 6 if you want to push mhz. Tweaked: 3


tWTR:
Large influence on stability / Small influence on bandwidth
From 10 to 8 didnt change results. 6 would lock up the system. This timing gives no bonus but affects stability a lot. Use with care.
Recommendation: Auto for oc/normal usage. 10 if you want to push mhz. Tweaked: 8(7)

tREF:
Small influence on stability / Small influence on bandwidth
Changing to 3,9us didnt show improvements in benchmark. It also didnt seem to affect stability. tREF was important with DDR1.
Recommendation: Auto for oc/normal usage. 7,8us if you want to push mhz. Tweaked: 3,9us


Command Rate:
Settings are 2T/1T. You probably already know a lot about this timing.
The 680i struggles running 1T above 800mhz. So do the ram - atleast 2,2v are needed. This timing gives a great boost to bandwidth, but is fairly hard to attain. I wont recommend any setting regarding this timing. You need to find what mhz you get with 1T, then find mhz with 2T, then compare benchmarks.

Ahh! Learning the relationships between the sub settings really made an impact-- I was tweaking them individually, without knowing that a+b should = C, etc.

This allowed me to pinch some timings even more and increased stability! I don't know how you were able to dig this much information up, but you sir, deserve a medal

 

[ivanlabrie]

Even though those are old it has some useful info...
Woomack can shed some more light on this I guess.

 

[Boulard83]

thanks ! This is still some good info to read and it apply to DDR3 but with higher timing.