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- Apr 22, 2005
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infinitevalence, great post and very helpful but I would reccomend removing FSB from the text unless refering to older XP ERA CPUs or Intel Hardware. All clocks with A64s, Optis and Newer Semprons (754,939,940,AM2...) come directly off the core clock. Some bios settings on some mobos still mention FSB like terms but the bios converts this to AMD standards behind the scenes. These behind the scene settings may be what causes YMMV in HTT max for some people. Ex: my BFG939 maxes at 260-261, DFI and others reach 280-300+.
http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_13041^13043,00.html
On AMD chips you have 4 busses. 1 Address to memory, 1 data to memory, 1 internal HTB(Bus and crossbar network) and 1 external HTT. Some may consider the extra external pins for MP procs to be a buss but they are handshake/control pins and that's beyond this scope. The memory bus is internally divided off of the divider that drives the internal HTB which is how you get DDR500 from HTB/HTT 250. Some may say it's simantics but it may also mean missing out on higher OC if you don't know what's really happening with these timings. As for the external HTT it runs from it's own 1x-5x divider based on the internal HTB. The external HTT is strictly SMP and for IO purposes and driving controller chips. The main reason that all settings run on that HTT number in your BIOS is to allow the internal HTB to run in sync with the HTT and Memory busses. You might ask, why would you bump the HTT for IO up by 4x or 5x. The answer is you have one processor with several IO devices and memory to deal with. Sending data to devices on a pumped up HTT allows the HTT contoller to service all these IO devices more effectively. The IO/South bridge handles the actual IO but the HTT directs where it's going. Also remember this is also designed for SMP which allows faster than internal buss transfers and better efficiencies than the competition. Memory also allows a bump up which is now in line for newer memory technology which even with higher latancies is still a slightly better preformance since it's one hop on the databus from memory to HT and one hop to cash. Expect to see better memory that AM2 will take advantage of.
IMO, memory is being held back until Intel can get better NB chips and CPUs to market.
http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_13041^13043,00.html
On AMD chips you have 4 busses. 1 Address to memory, 1 data to memory, 1 internal HTB(Bus and crossbar network) and 1 external HTT. Some may consider the extra external pins for MP procs to be a buss but they are handshake/control pins and that's beyond this scope. The memory bus is internally divided off of the divider that drives the internal HTB which is how you get DDR500 from HTB/HTT 250. Some may say it's simantics but it may also mean missing out on higher OC if you don't know what's really happening with these timings. As for the external HTT it runs from it's own 1x-5x divider based on the internal HTB. The external HTT is strictly SMP and for IO purposes and driving controller chips. The main reason that all settings run on that HTT number in your BIOS is to allow the internal HTB to run in sync with the HTT and Memory busses. You might ask, why would you bump the HTT for IO up by 4x or 5x. The answer is you have one processor with several IO devices and memory to deal with. Sending data to devices on a pumped up HTT allows the HTT contoller to service all these IO devices more effectively. The IO/South bridge handles the actual IO but the HTT directs where it's going. Also remember this is also designed for SMP which allows faster than internal buss transfers and better efficiencies than the competition. Memory also allows a bump up which is now in line for newer memory technology which even with higher latancies is still a slightly better preformance since it's one hop on the databus from memory to HT and one hop to cash. Expect to see better memory that AM2 will take advantage of.
IMO, memory is being held back until Intel can get better NB chips and CPUs to market.