Can someone help me with this matter.
I'm using 2x1Gb Super Talent cl3 memory on NF4 SLI mbo.
I must admit I'm not an expert in memory timings special alpha timings so I would apriciate any help I can get.
Here is everest list:
Dual Channel (128 bit)
CAS Latency (CL) 3T
RAS To CAS Delay (tRCD) 4T
RAS Precharge (tRP) 6T skip this one
RAS Active Time (tRAS) 8T
Row Cycle Time (tRC) 11T
Row Refresh Cycle Time (tRFC) 14T
Command Rate (CR) 1T
RAS To RAS Delay (tRRD) 2T
Write Recovery Time (tWR) 2T
Read To Write Delay (tRTW) 4T
Write To Read Delay (tWTR) 2T
Write CAS Latency (tWCL) 1T
Refresh Period (tREF) 166 MHz 7.8 us
DQS Skew Control Not used
DRAM Drive Strength Weak
DRAM Data Drive Strength 4 (No Reduction)
Max Async Latency 7 ns
Read Preamble Time 5.5 ns
Idle Cycle Limit 16
Dynamic Idle Cycle Counter Used
Read/Write Queue Bypass 8
Bypass Max 4
32-byte Granularity Not used
Note: tRP must stay at value of 6 nothing lower...long story caused by MBO
I'm using 2x1Gb Super Talent cl3 memory on NF4 SLI mbo.
I must admit I'm not an expert in memory timings special alpha timings so I would apriciate any help I can get.
Here is everest list:
Dual Channel (128 bit)
CAS Latency (CL) 3T
RAS To CAS Delay (tRCD) 4T
RAS Precharge (tRP) 6T skip this one
RAS Active Time (tRAS) 8T
Row Cycle Time (tRC) 11T
Row Refresh Cycle Time (tRFC) 14T
Command Rate (CR) 1T
RAS To RAS Delay (tRRD) 2T
Write Recovery Time (tWR) 2T
Read To Write Delay (tRTW) 4T
Write To Read Delay (tWTR) 2T
Write CAS Latency (tWCL) 1T
Refresh Period (tREF) 166 MHz 7.8 us
DQS Skew Control Not used
DRAM Drive Strength Weak
DRAM Data Drive Strength 4 (No Reduction)
Max Async Latency 7 ns
Read Preamble Time 5.5 ns
Idle Cycle Limit 16
Dynamic Idle Cycle Counter Used
Read/Write Queue Bypass 8
Bypass Max 4
32-byte Granularity Not used
Note: tRP must stay at value of 6 nothing lower...long story caused by MBO
